arm: v8: Move cpu init from crt0_64.S to start.S

Do init before secondary cpu jump.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Idd247743048907384d7f1ed13abf42403ae813d7

arm: crt0_64: Support enable Icache early for U-Boot proper

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I5db0b090cc675dd5adb2255250aff11cc97b0155

arm: crt0_64.S: don't require stack align access

That's too strict and it doesn't bring some benifits, let's disable it.
Stack align access issue was found in cpu_suspend().

Signed-off-by: Joseph C

arm: crt0_64.S: don't require stack align access

That's too strict and it doesn't bring some benifits, let's disable it.
Stack align access issue was found in cpu_suspend().

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I9442257b7bb1cf6bafa9de0b7da51d6ddb6ac150

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arm: crt0_64.S: disable arm64 SError for usbplug

On rk356x platform usbplug mode, we found it occurs SError
when rockusb download.

Issue dump:
.....
Serial: raw, 0xfe660000
dwmmc@fe2b0000: 1,

arm: crt0_64.S: disable arm64 SError for usbplug

On rk356x platform usbplug mode, we found it occurs SError
when rockusb download.

Issue dump:
.....
Serial: raw, 0xfe660000
dwmmc@fe2b0000: 1, dwmmc@fe2c0000: 2, sdhci@fe310000: 0
Bootdev: mmc 0
RKUSB: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x3a3e000
\"Error" handler, esr 0xbe000011

* Reason: Exception from SError interrupt
* PC = 0000000000013c68
* LR = 0000000000010f7c
.....

fixes:
(617c1bec46 arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I6270bd0a8afdd998ac09242f21598cc8acd200ca

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arm: crt0_64.S: don't set SCTLR.A=1

The CPU is able to execute load/store instruction on unaligned address,
and we don't need to avoid special alignment scene.

Now, SCTLR.A=1 causes U-Boot data-abo

arm: crt0_64.S: don't set SCTLR.A=1

The CPU is able to execute load/store instruction on unaligned address,
and we don't need to avoid special alignment scene.

Now, SCTLR.A=1 causes U-Boot data-abort while decompressing the LZ4 kernel.

Fixes: (b25dd131e0 arm: crt0_64: Enable sctlr A/SA bit for EL3/2/1)

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I25f85e10999afb0fbb42a742c39f61c00b8c6f70

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arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene

arm: v7/v8: Enable SError/Asynchronous external abort for TPL/SPL/U-Boot

Add this patch to support report SError/Asynchronous external abort
immediately in current exception level.

=== issue scene ===
When access a illegal address, It results in:
- read: Synchronous data-abort
- write: SError(64-bit)/Asynchronous external abort(32-bit)

=== 64-bit ===
EL3 SError ASynchronous exception in TPL/SPL was already
enabled in start.S and crt0_64.S which sets SCR_EL3.EA=1
and DAIF.A=0. We can test result of TPL/SPL by access address
0xfe108000 in rk3568.
Let's enable SError in U-Boot proper.

=== 32-bit ===
Let's set CPSR.A=0 to enable Asynchronous external abort, we can
test result by access address 0xfe808000 in rv1126.
Note: TPL/SPL vectors only provides "b ." for all exception entry.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Id9f660a9275f69fdc8443ad239aabf79682d95d0

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arm: crt0_64: Enable sctlr A/SA bit for EL3/2/1

Icache is enabled by default for TPL/SPL.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Idf613d816feb4766e1e1ab646cc88a86e6ca0982

dm: serial: support always use uart debug mode

In this mode, uart debug is initialized depends on
configuration from pre-loader or CONFIG_UART_DEBUG_.

The serial is not care about dts "stdout-path"

dm: serial: support always use uart debug mode

In this mode, uart debug is initialized depends on
configuration from pre-loader or CONFIG_UART_DEBUG_.

The serial is not care about dts "stdout-path" and
not register into console framework any more. It's
nice to use pre-loader serial and make serial easy
to configure.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: If4c68229d76b6f1710a35e3ef9a2a91cb306fa9c

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arm: lib: crt0_64: spl enables sctlr_el3 A/SA/I bits

A: Alignment check enable;
I: Instruction cache enable;
SA: Stack Alignment Check Enable;

Change-Id: Ic2a25dd23bc586540e177ea7e7927c24074180cc

arm: lib: crt0_64: spl enables sctlr_el3 A/SA/I bits

A: Alignment check enable;
I: Instruction cache enable;
SA: Stack Alignment Check Enable;

Change-Id: Ic2a25dd23bc586540e177ea7e7927c24074180cc
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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arm: add spl relocation support for armv8

Relocate spl itself to a high memory.

Change-Id: Ia69f05449a0a8e4f07cc6d37a2486c3cd2aa7176
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

arm64: enable async error handler

Enable the exception handler for async error so that we can get the
abort before kernel.

Change-Id: Ie0e7c89a0d03adf3b74b0d9ddf8c9117536dac6b
Signed-off-by: Kever

arm64: enable async error handler

Enable the exception handler for async error so that we can get the
abort before kernel.

Change-Id: Ie0e7c89a0d03adf3b74b0d9ddf8c9117536dac6b
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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common: support skip U-Boot relocation

Change-Id: I8640907204c82928c2fb07177835dc55a126aaf0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

serial: ns16550: support using pre-loader serial

- pass pre-loader serial configure by rk atags;
- it depends on serial aliases to find uart port;
- enabled by CONFIG_ROCKCHIP_USING_PRELOADER_SERIAL

serial: ns16550: support using pre-loader serial

- pass pre-loader serial configure by rk atags;
- it depends on serial aliases to find uart port;
- enabled by CONFIG_ROCKCHIP_USING_PRELOADER_SERIAL;

Change-Id: I6723cccc5e1f3dac77203b4cc19cdac631f5133b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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UPSTREAM: armv8: fix gd after relocation

Commit 21f4486faa5d ("armv8: update gd after relocate") sets x18
without checking the return value of spl_relocate_stack_gd().

Reviewed-by: Stephen Warren <

UPSTREAM: armv8: fix gd after relocation

Commit 21f4486faa5d ("armv8: update gd after relocate") sets x18
without checking the return value of spl_relocate_stack_gd().

Reviewed-by: Stephen Warren <swarren@nvidia.com>
Change-Id: I929a996608808934bf4d614acfffe43080594ecb
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Kever Yang <kever.yang@rock-chips.com>
CC: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit e421b646fce125ed92936628dc4b287de5f038a5)

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UPSTREAM: arm64: support running at addr other than linked to

This is required in the case where U-Boot is typically loaded and run at
a particular address, but for some reason the RAM at that locat

UPSTREAM: arm64: support running at addr other than linked to

This is required in the case where U-Boot is typically loaded and run at
a particular address, but for some reason the RAM at that location is not
available, e.g. due to memory fragmentation loading other boot binaries or
firmware, splitting an SMP complex between various different OSs without
using e.g. the EL2 second-stage page tables to hide the memory asignments,
or due to known ECC failures.

Change-Id: I2fd535325517921c6036188b74ab4facd37b7118
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 49e93875a62fb9e96a4a7483b9bd5d8ae27ea76e)

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ARMv8: get new GD address from gd->new_gd directly

the new GD address is calculated via board data BD currently
it require the new GD area locates below BD tightly, so a strict
constraint is imposed

ARMv8: get new GD address from gd->new_gd directly

the new GD address is calculated via board data BD currently
it require the new GD area locates below BD tightly, so a strict
constraint is imposed on memory layout which maybe make special
platform unpleasant.

fix it by getting new GD address from gd->new_gd directly.

Change-Id: I9fdfbbb13a7b0a572d7aa8394f754148c6285669
Signed-off-by: zijun_hu <zijun_hu@htc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 01a835998935b78c31e80227358ac11212d60878)

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armv8: update gd after relocate

We need to update gd in assamble code after relocate,
this is a fix to:
adc421e arm: move gd handling outside of C code

Change-Id: I2730d6e7a8f0ee2a2fb44d63dfc7991aa

armv8: update gd after relocate

We need to update gd in assamble code after relocate,
this is a fix to:
adc421e arm: move gd handling outside of C code

Change-Id: I2730d6e7a8f0ee2a2fb44d63dfc7991aaae733b7
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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Merge branch 'master' of git://git.denx.de/u-boot-rockchip

armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK

Now that TPL_STACK has been moved off the whitelist (ok, I'm lying:
the 'moving off the whitelist' part comes in once

armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK

Now that TPL_STACK has been moved off the whitelist (ok, I'm lying:
the 'moving off the whitelist' part comes in once moveconfig
runs... which will be a few commits down the line) and added to
Kconfig, we need to test CONFIG_TPL_NEEDS_SEPARATE_STACK to see
whether the value from TPL_STACK should be used or whether we try to
inherit whatever SPL uses.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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armv8: spl: Support separate stack for TPL

To allow a TPL and SPL to run from different addresses/memories, we
need to split setup of the TPL and SPL stacks. To do so, we introduce
CONFIG_TPL_STACK

armv8: spl: Support separate stack for TPL

To allow a TPL and SPL to run from different addresses/memories, we
need to split setup of the TPL and SPL stacks. To do so, we introduce
CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override
the initial stack pointer for TPL.

To provide backward compatibility for existing boards, this is added
as an optional configuration item and the normal search order (i.e.
SPL_STACK, then SYS_STACK) apply if not defined.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

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armv8: spl: Call spl_relocate_stack_gd for ARMv8

As part of the startup process for boards using the SPL, we need to
call spl_relocate_stack_gd. This is needed to set up malloc with its
DRAM buffer.

armv8: spl: Call spl_relocate_stack_gd for ARMv8

As part of the startup process for boards using the SPL, we need to
call spl_relocate_stack_gd. This is needed to set up malloc with its
DRAM buffer.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm64: use store with auto-increment

Save one instruction.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

arm64: use xzr to zero-out the bss section

AArch64 has a zero register (xzr). Use it instead of x2.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chr

arm64: use xzr to zero-out the bss section

AArch64 has a zero register (xzr). Use it instead of x2.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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armv8: spl: Call board_init_r from crt0_64 in SPL

As part of the startup process for boards using the SPL, the
meaning of board_init_f changed such that it should return normally
rather than calling

armv8: spl: Call board_init_r from crt0_64 in SPL

As part of the startup process for boards using the SPL, the
meaning of board_init_f changed such that it should return normally
rather than calling board_init_r directly. (see
db910353a126d84fe8dff7a694ea792f50fcfb6a )
This was fixed in 32-bit arm, but broke when SPL was added to
64 bit arm. This fixes crt0_64 so that it calls board_init_r
during the SPL and removes the direct call from board_init_f
from the arm SPL example.

Signed-off-by: Jeremy Hunt <Jeremy.Hunt@DEShawResearch.com>

Acked-by: Simon Glass <sjg@chromium.org>

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arm: initialize gd for AArch64

Commit adc421e4cee8 "arm: move gd handling outside of C code" removed
the call to arch_setup_gd() on ARM and replaced it with assembly code
in crt0.S. However, AArch64

arm: initialize gd for AArch64

Commit adc421e4cee8 "arm: move gd handling outside of C code" removed
the call to arch_setup_gd() on ARM and replaced it with assembly code
in crt0.S. However, AArch64 uses a different startup file, and the same
change was not made to it. This leaves gd uninitialized on AArch64, which
typically leads to hangs or crashes. This change fixes that.

Fixes: adc421e4cee8 ("arm: move gd handling outside of C code")
Signed-off-by: Stephen Warren <swarren@nvidia.com>

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