1eae4988bSStefano Babic/* 2eae4988bSStefano Babic * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 3eae4988bSStefano Babic * 4eae4988bSStefano Babic * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5eae4988bSStefano Babic * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7eae4988bSStefano Babic */ 8eae4988bSStefano Babic 9eae4988bSStefano Babic#include <config.h> 10eae4988bSStefano Babic#include <asm/arch/imx-regs.h> 11a4814a69SStefano Babic#include <generated/asm-offsets.h> 12eae4988bSStefano Babic#include "mx35pdk.h" 13151d63cbSBenoît Thébaudeau#include <asm/arch/lowlevel_macro.S> 14eae4988bSStefano Babic 15eae4988bSStefano Babic/* 16eae4988bSStefano Babic * return soc version 17eae4988bSStefano Babic * 0x10: TO1 18eae4988bSStefano Babic * 0x20: TO2 19eae4988bSStefano Babic * 0x30: TO3 20eae4988bSStefano Babic */ 21eae4988bSStefano Babic.macro check_soc_version ret, tmp 22eae4988bSStefano Babic ldr \tmp, =IIM_BASE_ADDR 23eae4988bSStefano Babic ldr \ret, [\tmp, #IIM_SREV] 24eae4988bSStefano Babic cmp \ret, #0x00 25eae4988bSStefano Babic moveq \tmp, #ROMPATCH_REV 26eae4988bSStefano Babic ldreq \ret, [\tmp] 27eae4988bSStefano Babic moveq \ret, \ret, lsl #4 28eae4988bSStefano Babic addne \ret, \ret, #0x10 29eae4988bSStefano Babic.endm 30eae4988bSStefano Babic 31eae4988bSStefano Babic/* CPLD on CS5 setup */ 32eae4988bSStefano Babic.macro init_debug_board 33eae4988bSStefano Babic ldr r0, =DBG_BASE_ADDR 34eae4988bSStefano Babic ldr r1, =DBG_CSCR_U_CONFIG 35eae4988bSStefano Babic str r1, [r0, #0x00] 36eae4988bSStefano Babic ldr r1, =DBG_CSCR_L_CONFIG 37eae4988bSStefano Babic str r1, [r0, #0x04] 38eae4988bSStefano Babic ldr r1, =DBG_CSCR_A_CONFIG 39eae4988bSStefano Babic str r1, [r0, #0x08] 40eae4988bSStefano Babic.endm 41eae4988bSStefano Babic 42eae4988bSStefano Babic/* clock setup */ 43eae4988bSStefano Babic.macro init_clock 44eae4988bSStefano Babic ldr r0, =CCM_BASE_ADDR 45eae4988bSStefano Babic 46eae4988bSStefano Babic /* default CLKO to 1/32 of the ARM core*/ 47eae4988bSStefano Babic ldr r1, [r0, #CLKCTL_COSR] 48eae4988bSStefano Babic bic r1, r1, #0x00000FF00 49eae4988bSStefano Babic bic r1, r1, #0x0000000FF 50eae4988bSStefano Babic mov r2, #0x00006C00 51eae4988bSStefano Babic add r2, r2, #0x67 52eae4988bSStefano Babic orr r1, r1, r2 53eae4988bSStefano Babic str r1, [r0, #CLKCTL_COSR] 54eae4988bSStefano Babic 55eae4988bSStefano Babic ldr r2, =CCM_CCMR_CONFIG 56eae4988bSStefano Babic str r2, [r0, #CLKCTL_CCMR] 57eae4988bSStefano Babic 58eae4988bSStefano Babic check_soc_version r1, r2 59eae4988bSStefano Babic cmp r1, #CHIP_REV_2_0 60eae4988bSStefano Babic ldrhs r3, =CCM_MPLL_532_HZ 61eae4988bSStefano Babic bhs 1f 62eae4988bSStefano Babic ldr r2, [r0, #CLKCTL_PDR0] 63eae4988bSStefano Babic tst r2, #CLKMODE_CONSUMER 64eae4988bSStefano Babic ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ 65eae4988bSStefano Babic ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ 66eae4988bSStefano Babic1: 67eae4988bSStefano Babic str r3, [r0, #CLKCTL_MPCTL] 68eae4988bSStefano Babic 69eae4988bSStefano Babic ldr r1, =CCM_PPLL_300_HZ 70eae4988bSStefano Babic str r1, [r0, #CLKCTL_PPCTL] 71eae4988bSStefano Babic 72eae4988bSStefano Babic ldr r1, =CCM_PDR0_CONFIG 73eae4988bSStefano Babic bic r1, r1, #0x800000 74eae4988bSStefano Babic str r1, [r0, #CLKCTL_PDR0] 75eae4988bSStefano Babic 76eae4988bSStefano Babic ldr r1, [r0, #CLKCTL_CGR0] 77eae4988bSStefano Babic orr r1, r1, #0x0C300000 78eae4988bSStefano Babic str r1, [r0, #CLKCTL_CGR0] 79eae4988bSStefano Babic 80eae4988bSStefano Babic ldr r1, [r0, #CLKCTL_CGR1] 81eae4988bSStefano Babic orr r1, r1, #0x00000C00 82eae4988bSStefano Babic orr r1, r1, #0x00000003 83eae4988bSStefano Babic str r1, [r0, #CLKCTL_CGR1] 84961a7628SBenoît Thébaudeau 85961a7628SBenoît Thébaudeau ldr r1, [r0, #CLKCTL_CGR2] 86961a7628SBenoît Thébaudeau orr r1, r1, #0x00C00000 87961a7628SBenoît Thébaudeau str r1, [r0, #CLKCTL_CGR2] 88eae4988bSStefano Babic.endm 89eae4988bSStefano Babic 90eae4988bSStefano Babic.macro setup_sdram 91eae4988bSStefano Babic ldr r0, =ESDCTL_BASE_ADDR 92eae4988bSStefano Babic mov r3, #0x2000 93eae4988bSStefano Babic str r3, [r0, #0x0] 94eae4988bSStefano Babic str r3, [r0, #0x8] 95eae4988bSStefano Babic 96eae4988bSStefano Babic /*ip(r12) has used to save lr register in upper calling*/ 97eae4988bSStefano Babic mov fp, lr 98eae4988bSStefano Babic 99eae4988bSStefano Babic mov r5, #0x00 100eae4988bSStefano Babic mov r2, #0x00 101eae4988bSStefano Babic mov r1, #CSD0_BASE_ADDR 102eae4988bSStefano Babic bl setup_sdram_bank 1036b5acfc1SStefano Babic 1046b5acfc1SStefano Babic mov r5, #0x00 1056b5acfc1SStefano Babic mov r2, #0x00 1066b5acfc1SStefano Babic mov r1, #CSD1_BASE_ADDR 1076b5acfc1SStefano Babic bl setup_sdram_bank 108eae4988bSStefano Babic 109eae4988bSStefano Babic mov lr, fp 110eae4988bSStefano Babic 111eae4988bSStefano Babic1: 112eae4988bSStefano Babic ldr r3, =ESDCTL_DELAY_LINE5 113eae4988bSStefano Babic str r3, [r0, #0x30] 114eae4988bSStefano Babic.endm 115eae4988bSStefano Babic 116eae4988bSStefano Babic.globl lowlevel_init 117eae4988bSStefano Babiclowlevel_init: 118eae4988bSStefano Babic mov r10, lr 119eae4988bSStefano Babic 120151d63cbSBenoît Thébaudeau core_init 121eae4988bSStefano Babic 122eae4988bSStefano Babic init_aips 123eae4988bSStefano Babic 124eae4988bSStefano Babic init_max 125eae4988bSStefano Babic 126eae4988bSStefano Babic init_m3if 127eae4988bSStefano Babic 128eae4988bSStefano Babic init_clock 129eae4988bSStefano Babic init_debug_board 130eae4988bSStefano Babic 131eae4988bSStefano Babic cmp pc, #PHYS_SDRAM_1 132eae4988bSStefano Babic blo init_sdram_start 133eae4988bSStefano Babic cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) 134eae4988bSStefano Babic blo skip_sdram_setup 135eae4988bSStefano Babic 136eae4988bSStefano Babicinit_sdram_start: 137eae4988bSStefano Babic /*init_sdram*/ 138eae4988bSStefano Babic setup_sdram 139eae4988bSStefano Babic 140eae4988bSStefano Babicskip_sdram_setup: 141eae4988bSStefano Babic mov lr, r10 142eae4988bSStefano Babic mov pc, lr 143eae4988bSStefano Babic 144eae4988bSStefano Babic 145eae4988bSStefano Babic/* 146eae4988bSStefano Babic * r0: ESDCTL control base, r1: sdram slot base 147eae4988bSStefano Babic * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base 148eae4988bSStefano Babic */ 149eae4988bSStefano Babicsetup_sdram_bank: 150eae4988bSStefano Babic mov r3, #0xE 151eae4988bSStefano Babic tst r2, #0x1 152eae4988bSStefano Babic orreq r3, r3, #0x300 /*DDR2*/ 153eae4988bSStefano Babic str r3, [r0, #0x10] 154eae4988bSStefano Babic bic r3, r3, #0x00A 155eae4988bSStefano Babic str r3, [r0, #0x10] 156eae4988bSStefano Babic beq 2f 157eae4988bSStefano Babic 158eae4988bSStefano Babic mov r3, #0x20000 159eae4988bSStefano Babic1: subs r3, r3, #1 160eae4988bSStefano Babic bne 1b 161eae4988bSStefano Babic 162eae4988bSStefano Babic2: tst r2, #0x1 163eae4988bSStefano Babic ldreq r3, =ESDCTL_DDR2_CONFIG 164eae4988bSStefano Babic ldrne r3, =ESDCTL_MDDR_CONFIG 165eae4988bSStefano Babic cmp r1, #CSD1_BASE_ADDR 166eae4988bSStefano Babic strlo r3, [r0, #0x4] 167eae4988bSStefano Babic strhs r3, [r0, #0xC] 168eae4988bSStefano Babic 169eae4988bSStefano Babic ldr r3, =ESDCTL_0x92220000 170eae4988bSStefano Babic strlo r3, [r0, #0x0] 171eae4988bSStefano Babic strhs r3, [r0, #0x8] 172eae4988bSStefano Babic mov r3, #0xDA 173eae4988bSStefano Babic ldr r4, =ESDCTL_PRECHARGE 174eae4988bSStefano Babic strb r3, [r1, r4] 175eae4988bSStefano Babic 176eae4988bSStefano Babic tst r2, #0x1 177eae4988bSStefano Babic bne skip_set_mode 178eae4988bSStefano Babic 179eae4988bSStefano Babic cmp r1, #CSD1_BASE_ADDR 180eae4988bSStefano Babic ldr r3, =ESDCTL_0xB2220000 181eae4988bSStefano Babic strlo r3, [r0, #0x0] 182eae4988bSStefano Babic strhs r3, [r0, #0x8] 183eae4988bSStefano Babic mov r3, #0xDA 184eae4988bSStefano Babic ldr r4, =ESDCTL_DDR2_EMR2 185eae4988bSStefano Babic strb r3, [r1, r4] 186eae4988bSStefano Babic ldr r4, =ESDCTL_DDR2_EMR3 187eae4988bSStefano Babic strb r3, [r1, r4] 188eae4988bSStefano Babic ldr r4, =ESDCTL_DDR2_EN_DLL 189eae4988bSStefano Babic strb r3, [r1, r4] 190eae4988bSStefano Babic ldr r4, =ESDCTL_DDR2_RESET_DLL 191eae4988bSStefano Babic strb r3, [r1, r4] 192eae4988bSStefano Babic 193eae4988bSStefano Babic ldr r3, =ESDCTL_0x92220000 194eae4988bSStefano Babic strlo r3, [r0, #0x0] 195eae4988bSStefano Babic strhs r3, [r0, #0x8] 196eae4988bSStefano Babic mov r3, #0xDA 197eae4988bSStefano Babic ldr r4, =ESDCTL_PRECHARGE 198eae4988bSStefano Babic strb r3, [r1, r4] 199eae4988bSStefano Babic 200eae4988bSStefano Babicskip_set_mode: 201eae4988bSStefano Babic cmp r1, #CSD1_BASE_ADDR 202eae4988bSStefano Babic ldr r3, =ESDCTL_0xA2220000 203eae4988bSStefano Babic strlo r3, [r0, #0x0] 204eae4988bSStefano Babic strhs r3, [r0, #0x8] 205eae4988bSStefano Babic mov r3, #0xDA 206eae4988bSStefano Babic strb r3, [r1] 207eae4988bSStefano Babic strb r3, [r1] 208eae4988bSStefano Babic 209eae4988bSStefano Babic ldr r3, =ESDCTL_0xB2220000 210eae4988bSStefano Babic strlo r3, [r0, #0x0] 211eae4988bSStefano Babic strhs r3, [r0, #0x8] 212eae4988bSStefano Babic tst r2, #0x1 213eae4988bSStefano Babic ldreq r4, =ESDCTL_DDR2_MR 214eae4988bSStefano Babic ldrne r4, =ESDCTL_MDDR_MR 215eae4988bSStefano Babic mov r3, #0xDA 216eae4988bSStefano Babic strb r3, [r1, r4] 217eae4988bSStefano Babic ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT 218eae4988bSStefano Babic streqb r3, [r1, r4] 219eae4988bSStefano Babic ldreq r4, =ESDCTL_DDR2_EN_DLL 220eae4988bSStefano Babic ldrne r4, =ESDCTL_MDDR_EMR 221eae4988bSStefano Babic strb r3, [r1, r4] 222eae4988bSStefano Babic 223eae4988bSStefano Babic cmp r1, #CSD1_BASE_ADDR 224eae4988bSStefano Babic ldr r3, =ESDCTL_0x82228080 225eae4988bSStefano Babic strlo r3, [r0, #0x0] 226eae4988bSStefano Babic strhs r3, [r0, #0x8] 227eae4988bSStefano Babic 228eae4988bSStefano Babic tst r2, #0x1 229eae4988bSStefano Babic moveq r4, #0x20000 230eae4988bSStefano Babic movne r4, #0x200 231eae4988bSStefano Babic1: subs r4, r4, #1 232eae4988bSStefano Babic bne 1b 233eae4988bSStefano Babic 234eae4988bSStefano Babic str r3, [r1, #0x100] 235eae4988bSStefano Babic ldr r4, [r1, #0x100] 236eae4988bSStefano Babic cmp r3, r4 237eae4988bSStefano Babic movne r3, #1 238eae4988bSStefano Babic moveq r3, #0 239eae4988bSStefano Babic 240eae4988bSStefano Babic mov pc, lr 241