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Searched refs:ccm (Results 1 – 25 of 91) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c24 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
39 C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg); in clock_init_safe()
43 &ccm->ahb0_cfg); in clock_init_safe()
46 &ccm->ahb1_cfg); in clock_init_safe()
49 &ccm->ahb2_cfg); in clock_init_safe()
52 &ccm->apb0_cfg); in clock_init_safe()
56 &ccm->gtbus_cfg); in clock_init_safe()
59 &ccm->cci400_cfg); in clock_init_safe()
62 setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); in clock_init_safe()
63 setbits_le32(&ccm->apb1_gate, (1 << 24)); in clock_init_safe()
[all …]
H A Dclock_sun8i_a83t.c22 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
27 writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); in clock_init_safe()
28 writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); in clock_init_safe()
29 while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} in clock_init_safe()
32 writel(0x0, &ccm->cci400_cfg); in clock_init_safe()
34 writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); in clock_init_safe()
38 clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, in clock_init_safe()
40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
41 while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} in clock_init_safe()
43 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); in clock_init_safe()
[all …]
H A Dclock_sun6i.c22 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
40 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); in clock_init_safe()
45 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
46 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) in clock_init_safe()
49 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); in clock_init_safe()
51 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); in clock_init_safe()
53 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); in clock_init_safe()
56 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); in clock_init_safe()
57 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
58 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
[all …]
H A Dclock_sun4i.c22 struct sunxi_ccm_reg * const ccm = in clock_init_safe() local
30 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
31 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); in clock_init_safe()
37 &ccm->cpu_ahb_apb0_cfg); in clock_init_safe()
39 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); in clock_init_safe()
41 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); in clock_init_safe()
43 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); in clock_init_safe()
44 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); in clock_init_safe()
51 struct sunxi_ccm_reg *const ccm = in clock_init_uart() local
58 &ccm->apb1_clk_div_cfg); in clock_init_uart()
[all …]
H A Dclock.c43 struct sunxi_ccm_reg *const ccm = in clock_twi_onoff() local
58 setbits_le32(&ccm->apb2_gate, in clock_twi_onoff()
60 setbits_le32(&ccm->apb2_reset_cfg, in clock_twi_onoff()
63 clrbits_le32(&ccm->apb2_reset_cfg, in clock_twi_onoff()
65 clrbits_le32(&ccm->apb2_gate, in clock_twi_onoff()
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx25/
H A Dgeneric.c55 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_mpllclk() local
58 return imx_decode_pll(readl(&ccm->mpctl), fref); in imx_get_mpllclk()
63 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_upllclk() local
66 return imx_decode_pll(readl(&ccm->upctl), fref); in imx_get_upllclk()
71 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_armclk() local
72 ulong cctl = readl(&ccm->cctl); in imx_get_armclk()
87 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_ahbclk() local
88 ulong cctl = readl(&ccm->cctl); in imx_get_ahbclk()
105 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; in imx_get_perclk() local
106 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() : in imx_get_perclk()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm1136/mx35/
H A Dgeneric.c134 struct ccm_regs *ccm = in get_mcu_main_clk() local
136 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); in get_mcu_main_clk()
137 fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK); in get_mcu_main_clk()
144 struct ccm_regs *ccm = in get_ipg_clk() local
146 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_clk()
154 struct ccm_regs *ccm = in get_ipg_per_clk() local
156 u32 pdr0 = readl(&ccm->pdr0); in get_ipg_per_clk()
157 u32 pdr4 = readl(&ccm->pdr4); in get_ipg_per_clk()
175 struct ccm_regs *ccm = in imx_get_uartclk() local
177 u32 pdr4 = readl(&ccm->pdr4); in imx_get_uartclk()
[all …]
/rk3399_rockchip-uboot/board/ccv/xpress/
H A Dspl.c82 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
84 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
85 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
86 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
87 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
88 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
89 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
90 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
91 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/rk3399_rockchip-uboot/drivers/usb/host/
H A Dohci-sunxi.c29 struct sunxi_ccm_reg *ccm; member
43 priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; in ohci_usb_probe()
44 if (IS_ERR(priv->ccm)) in ohci_usb_probe()
45 return PTR_ERR(priv->ccm); in ohci_usb_probe()
64 setbits_le32(&priv->ccm->ahb_gate0, in ohci_usb_probe()
66 setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask); in ohci_usb_probe()
68 setbits_le32(&priv->ccm->ahb_reset0_cfg, in ohci_usb_probe()
90 clrbits_le32(&priv->ccm->ahb_reset0_cfg, priv->ahb_gate_mask); in ohci_usb_remove()
92 clrbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask); in ohci_usb_remove()
93 clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask); in ohci_usb_remove()
H A Dehci-sunxi.c30 struct sunxi_ccm_reg *ccm; member
43 priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; in ehci_usb_probe()
44 if (IS_ERR(priv->ccm)) in ehci_usb_probe()
45 return PTR_ERR(priv->ccm); in ehci_usb_probe()
60 setbits_le32(&priv->ccm->ahb_gate0, in ehci_usb_probe()
63 setbits_le32(&priv->ccm->ahb_reset0_cfg, in ehci_usb_probe()
88 clrbits_le32(&priv->ccm->ahb_reset0_cfg, priv->ahb_gate_mask); in ehci_usb_remove()
90 clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask); in ehci_usb_remove()
/rk3399_rockchip-uboot/board/CarMediaLab/flea3/
H A Dflea3.c135 struct ccm_regs *ccm = in board_early_init_f() local
143 writel(CCM_CCMR_CONFIG, &ccm->ccmr); in board_early_init_f()
145 writel(CCM_MPLL_532_HZ, &ccm->mpctl); in board_early_init_f()
146 writel(CCM_PPLL_300_HZ, &ccm->ppctl); in board_early_init_f()
149 writel(0x00001000, &ccm->pdr0); in board_early_init_f()
155 writel(readl(&ccm->cgr0) | in board_early_init_f()
159 &ccm->cgr0); in board_early_init_f()
161 writel(readl(&ccm->cgr1) | in board_early_init_f()
169 &ccm->cgr1); in board_early_init_f()
172 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); in board_early_init_f()
/rk3399_rockchip-uboot/board/barco/platinum/
H A Dplatinum.h67 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
69 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
70 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
71 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
72 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
73 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ in ccgr_init()
74 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
75 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/rk3399_rockchip-uboot/board/aristainetos/
H A Daristainetos-v2.c407 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in enable_lvds() local
412 reg = readl(&ccm->analog_pll_video); in enable_lvds()
414 writel(reg, &ccm->analog_pll_video); in enable_lvds()
421 writel(reg, &ccm->analog_pll_video); in enable_lvds()
424 &ccm->analog_pll_video_num); in enable_lvds()
426 &ccm->analog_pll_video_denom); in enable_lvds()
429 writel(reg, &ccm->analog_pll_video); in enable_lvds()
432 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in enable_lvds()
437 reg = readl(&ccm->analog_pll_video); in enable_lvds()
440 writel(reg, &ccm->analog_pll_video); in enable_lvds()
[all …]
/rk3399_rockchip-uboot/board/freescale/vf610twr/
H A Dvf610twr.c271 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in clock_init() local
274 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
276 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
278 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
283 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
285 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
288 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
290 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
292 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
294 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c32 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
46 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
50 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
59 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
63 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
73 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5441x_clocks() local
77 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; in setup_5441x_clocks()
105 setbits_be16(&ccm->misccr2, 0x02); in setup_5441x_clocks()
118 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */ in setup_5441x_clocks()
130 ccm_t *ccm = (ccm_t *)MMAP_CCM; in setup_5445x_clocks() local
[all …]
/rk3399_rockchip-uboot/board/toradex/colibri_vf/
H A Dcolibri_vf.c386 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in clock_init() local
390 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, in clock_init()
393 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); in clock_init()
395 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, in clock_init()
397 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, in clock_init()
401 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, in clock_init()
403 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, in clock_init()
406 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, in clock_init()
408 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, in clock_init()
410 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, in clock_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dlitesom.c150 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
152 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
153 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
154 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
155 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
156 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
157 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
158 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
159 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c27 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in enable_ocotp_clk() local
30 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
35 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
41 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_mcu_main_clk() local
46 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
50 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
105 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_bus_clk() local
108 ccm_cacrr = readl(&ccm->cacrr); in get_bus_clk()
119 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; in get_ipg_clk() local
122 ccm_cacrr = readl(&ccm->cacrr); in get_ipg_clk()
[all …]
/rk3399_rockchip-uboot/board/solidrun/mx6cuboxi/
H A Dmx6cuboxi.c238 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
246 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); in setup_display()
248 reg = readl(&ccm->analog_pll_video); in setup_display()
253 writel(reg, &ccm->analog_pll_video); in setup_display()
255 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); in setup_display()
256 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); in setup_display()
259 writel(reg, &ccm->analog_pll_video); in setup_display()
262 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in setup_display()
269 reg = readl(&ccm->analog_pll_video); in setup_display()
272 writel(reg, &ccm->analog_pll_video); in setup_display()
[all …]
/rk3399_rockchip-uboot/board/engicam/common/
H A Dspl.c325 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
328 writel(0x00003F3F, &ccm->CCGR0); in ccgr_init()
329 writel(0x0030FC00, &ccm->CCGR1); in ccgr_init()
330 writel(0x000FC000, &ccm->CCGR2); in ccgr_init()
331 writel(0x3F300000, &ccm->CCGR3); in ccgr_init()
332 writel(0xFF00F300, &ccm->CCGR4); in ccgr_init()
333 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
334 writel(0x000003CC, &ccm->CCGR6); in ccgr_init()
336 writel(0x00c03f3f, &ccm->CCGR0); in ccgr_init()
337 writel(0xfcffff00, &ccm->CCGR1); in ccgr_init()
[all …]
/rk3399_rockchip-uboot/board/sunxi/
H A Dgmac.c12 struct sunxi_ccm_reg *const ccm = in eth_init_board() local
17 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); in eth_init_board()
18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); in eth_init_board()
20 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); in eth_init_board()
25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | in eth_init_board()
27 setbits_le32(&ccm->gmac_clk_cfg, in eth_init_board()
30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | in eth_init_board()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf532x/
H A Dspeed.c53 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in get_sys_clock() local
58 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { in get_sys_clock()
59 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); in get_sys_clock()
91 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_limp() local
101 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); in clock_limp()
104 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); in clock_limp()
106 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_limp()
114 ccm_t *ccm = (ccm_t *)(MMAP_CCM); in clock_exit_limp() local
118 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
121 while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK)) in clock_exit_limp()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c32 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_enter_limp() local
45 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); in clock_enter_limp()
48 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_enter_limp()
57 ccm_t *ccm = (ccm_t *)MMAP_CCM; in clock_exit_limp() local
61 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); in clock_exit_limp()
74 ccm_t *ccm = (ccm_t *)MMAP_CCM; in get_clocks() local
108 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { in get_clocks()
/rk3399_rockchip-uboot/board/liebherr/display5/
H A Dspl.c107 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in ccgr_init() local
109 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
110 writel(0x0030FC3F, &ccm->CCGR1); in ccgr_init()
111 writel(0x0FFFCFC0, &ccm->CCGR2); in ccgr_init()
112 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
113 writel(0x00FFF300, &ccm->CCGR4); in ccgr_init()
114 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
115 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/rk3399_rockchip-uboot/board/tbs/tbs2910/
H A Dtbs2910.c305 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; in setup_display() local
313 reg = readl(&ccm->analog_pll_video); in setup_display()
315 writel(reg, &ccm->analog_pll_video); in setup_display()
321 writel(reg, &ccm->analog_pll_video); in setup_display()
323 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); in setup_display()
324 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); in setup_display()
327 writel(reg, &ccm->analog_pll_video); in setup_display()
330 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) in setup_display()
335 reg = readl(&ccm->analog_pll_video); in setup_display()
338 writel(reg, &ccm->analog_pll_video); in setup_display()
[all …]

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