15d6050fdSStefan Roese /* 25d6050fdSStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 35d6050fdSStefan Roese * 45d6050fdSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 55d6050fdSStefan Roese */ 65d6050fdSStefan Roese 75d6050fdSStefan Roese #ifndef _PLATINUM_H_ 85d6050fdSStefan Roese #define _PLATINUM_H_ 95d6050fdSStefan Roese 105d6050fdSStefan Roese #include <miiphy.h> 115d6050fdSStefan Roese #include <asm/arch/crm_regs.h> 12*5ba49e75SStefano Babic #include <asm/io.h> 135d6050fdSStefan Roese 145d6050fdSStefan Roese /* Defines */ 155d6050fdSStefan Roese 165d6050fdSStefan Roese #define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ 175d6050fdSStefan Roese PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ 185d6050fdSStefan Roese PAD_CTL_HYS) 195d6050fdSStefan Roese #define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ 205d6050fdSStefan Roese PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 215d6050fdSStefan Roese PAD_CTL_HYS) 225d6050fdSStefan Roese #define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ 235d6050fdSStefan Roese PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ 245d6050fdSStefan Roese PAD_CTL_HYS) 255d6050fdSStefan Roese #define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ 265d6050fdSStefan Roese PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ 275d6050fdSStefan Roese PAD_CTL_HYS) 285d6050fdSStefan Roese #define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \ 295d6050fdSStefan Roese PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ 305d6050fdSStefan Roese PAD_CTL_HYS) 315d6050fdSStefan Roese 325d6050fdSStefan Roese #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 335d6050fdSStefan Roese PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 345d6050fdSStefan Roese 355d6050fdSStefan Roese #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 365d6050fdSStefan Roese PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 375d6050fdSStefan Roese PAD_CTL_ODE | PAD_CTL_SRE_FAST) 385d6050fdSStefan Roese #define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 395d6050fdSStefan Roese PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ 405d6050fdSStefan Roese PAD_CTL_ODE | PAD_CTL_SRE_SLOW) 415d6050fdSStefan Roese 425d6050fdSStefan Roese #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 435d6050fdSStefan Roese PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ 445d6050fdSStefan Roese PAD_CTL_HYS) 455d6050fdSStefan Roese 465d6050fdSStefan Roese #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 475d6050fdSStefan Roese PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ 485d6050fdSStefan Roese PAD_CTL_HYS) 495d6050fdSStefan Roese 505d6050fdSStefan Roese 515d6050fdSStefan Roese #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 525d6050fdSStefan Roese #define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL) 535d6050fdSStefan Roese 545d6050fdSStefan Roese /* Prototypes */ 555d6050fdSStefan Roese 565d6050fdSStefan Roese int platinum_setup_enet(void); 575d6050fdSStefan Roese int platinum_setup_i2c(void); 585d6050fdSStefan Roese int platinum_setup_spi(void); 595d6050fdSStefan Roese int platinum_setup_uart(void); 605d6050fdSStefan Roese int platinum_phy_config(struct phy_device *phydev); 615d6050fdSStefan Roese int platinum_init_gpio(void); 625d6050fdSStefan Roese int platinum_init_usb(void); 635d6050fdSStefan Roese int platinum_init_finished(void); 645d6050fdSStefan Roese ccgr_init(void)655d6050fdSStefan Roesestatic inline void ccgr_init(void) 665d6050fdSStefan Roese { 675d6050fdSStefan Roese struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 685d6050fdSStefan Roese 695d6050fdSStefan Roese writel(0x00C03F3F, &ccm->CCGR0); 705d6050fdSStefan Roese writel(0x0030FC03, &ccm->CCGR1); 715d6050fdSStefan Roese writel(0x0FFFC000, &ccm->CCGR2); 725d6050fdSStefan Roese writel(0x3FF00000, &ccm->CCGR3); 735d6050fdSStefan Roese writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ 745d6050fdSStefan Roese writel(0x0F0000C3, &ccm->CCGR5); 755d6050fdSStefan Roese writel(0x000003FF, &ccm->CCGR6); 765d6050fdSStefan Roese } 775d6050fdSStefan Roese 785d6050fdSStefan Roese #endif /* _PLATINUM_H_ */ 79