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Searched refs:PLL (Results 1 – 25 of 38) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/at91/
H A DKconfig9 PLLA, UTMI PLL. Clocks can also be a source clock of other
16 bool "Support UTMI PLL Clock"
19 This option is used to enable the AT91 UTMI PLL clock
21 output of 480 MHz UTMI PLL, The souce clock of the UTMI
22 PLL is the main clock, so the main clock must select the
/rk3399_rockchip-uboot/doc/
H A DREADME.imx59 1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
12 The PLL's in the i.MX51 processor can go out of lock due to a metastable
14 This workaround implements an undocumented feature in the PLL (dither
H A DREADME.Heterogeneous-SoCs63 Following are the defines for PLL's index that provide the Clocking to
66 CONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock
67 CONFIG_SYS_ULB_CLK - Define PLL index for ULB clock
68 CONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock
H A DREADME.m68k144 -- defines the PLL Multiplication Factor Devider
146 CONFIG_SYS_RFD -- defines the PLL Reduce Frecuency Devider
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A DKconfig2 bool "Rockchip PLL clock drivers"
H A Dclk_rk1808.c80 [APLL] = PLL(pll_rk3036, PLL_APLL, RK1808_PLL_CON(0),
82 [DPLL] = PLL(pll_rk3036, PLL_DPLL, RK1808_PLL_CON(8),
84 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK1808_PLL_CON(16),
86 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK1808_PLL_CON(24),
88 [NPLL] = PLL(pll_rk3036, PLL_NPLL, RK1808_PLL_CON(32),
90 [PPLL] = PLL(pll_rk3036, PLL_PPLL, RK1808_PMU_PLL_CON(0),
H A Dclk_rk3128.c81 [APLL] = PLL(pll_rk3036, PLL_APLL, RK2928_PLL_CON(0),
83 [DPLL] = PLL(pll_rk3036, PLL_DPLL, RK2928_PLL_CON(4),
85 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(8),
87 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(12),
H A Dclk_rk3328.c106 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3328_PLL_CON(0),
108 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3328_PLL_CON(8),
110 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3328_PLL_CON(16),
112 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3328_PLL_CON(24),
114 [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3328_PLL_CON(40),
H A Dclk_rk3588.c48 [B0PLL] = PLL(pll_rk3588, PLL_B0PLL, RK3588_B0_PLL_CON(0),
51 [B1PLL] = PLL(pll_rk3588, PLL_B1PLL, RK3588_B1_PLL_CON(8),
54 [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3588_LPLL_CON(16),
56 [V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),
58 [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3588_PLL_CON(96),
60 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),
62 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),
64 [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),
66 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
H A Dclk_rk322x.c82 [APLL] = PLL(pll_rk3036, PLL_APLL, RK2928_PLL_CON(0),
84 [DPLL] = PLL(pll_rk3036, PLL_DPLL, RK2928_PLL_CON(3),
86 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(6),
88 [GPLL] = PLL(pll_rk3036, PLL_GPLL, RK2928_PLL_CON(9),
H A Dclk_rk3308.c76 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
80 [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
82 [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
H A Dclk_rk3562.c47 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3562_PLL_CON(0),
49 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3562_PLL_CON(24),
51 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
53 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3562_PLL_CON(40),
55 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3562_PMU1_PLL_CON(0),
57 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3562_SUBDDR_PLL_CON(0),
H A Dclk_rk3576.c66 [BPLL] = PLL(pll_rk3588, PLL_BPLL, RK3576_PLL_CON(0),
69 [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3576_LPLL_CON(16),
71 [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88),
73 [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3576_PLL_CON(96),
75 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3576_PLL_CON(104),
77 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3576_PLL_CON(112),
79 [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128),
H A Dclk_rv1106.c39 [APLL] = PLL(pll_rk3328, PLL_APLL, RV1106_PLL_CON(0),
41 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1106_PLL_CON(16),
43 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1106_PLL_CON(8),
45 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1106_PLL_CON(24),
H A Dclk_rk3528.c66 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
69 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
72 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
75 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
H A Dclk_rk3568.c68 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3568_PLL_CON(0),
70 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3568_PLL_CON(8),
72 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
74 [GPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PLL_CON(16),
76 [NPLL] = PLL(pll_rk3328, PLL_NPLL, RK3568_PLL_CON(32),
78 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
80 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3568_PMU_PLL_CON(0),
82 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PMU_PLL_CON(16),
/rk3399_rockchip-uboot/board/freescale/mpc832xemds/
H A DREADME28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
32 SW7[1-8]= 1000_0011 (QE PLL setting)
/rk3399_rockchip-uboot/board/freescale/mpc837xemds/
H A DREADME27 SW4[1-8]= 0000_0110 (core PLL setting)
28 SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/
H A Dqts-filter.sh108 * Altera SoCFPGA Clock and PLL configuration
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h55 #define PLL(_type, _id, _con, _mode, _mshift, \ macro
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A DKconfig292 This number is the reference clock frequency of core PLL.
293 For most platforms, the core PLL and Platform PLL have the same
304 Platform PLL, in another word:
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/
H A DKconfig70 PLL, Low-Power, and Reset Control Register (15-30)
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Dexynos_mipi_dsi.txt29 samsung,dsim-config-pll-stable-time: the PLL Timer for stability
/rk3399_rockchip-uboot/arch/arm/mach-mvebu/
H A DKconfig46 # Armada PLL frequency (used for NAND clock generation)
/rk3399_rockchip-uboot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg119 ; the system PLL and the peripheral's clocks are changed together.

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