| /rk3399_rockchip-uboot/arch/arm/mach-rmobile/ |
| H A D | lowlevel_init_gen3.S | 27 ldr x0, =GICD_BASE
34 ldr x0, =GICD_BASE
41 ldr x0, =GICD_BASE
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | config.h | 49 #define GICD_BASE 0x06000000 macro
159 #define GICD_BASE 0x01401000 macro
187 #define GICD_BASE 0x01401000 macro
217 #define GICD_BASE 0x01410000 macro
|
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | vexpress_aemv8a.h | 88 #define GICD_BASE (0x2f000000) macro
94 #define GICD_BASE (0x2f000000) macro
97 #define GICD_BASE (0x2C010000) macro
|
| H A D | sun50i.h | 21 #define GICD_BASE 0x1c81000 macro
|
| H A D | rk322x_common.h | 24 #define GICD_BASE 0x32011000 macro
|
| H A D | rk3368_common.h | 36 #define GICD_BASE 0xffB71000 macro
|
| H A D | rk3328_common.h | 28 #define GICD_BASE 0xFF811000 macro
|
| H A D | rk3128_common.h | 23 #define GICD_BASE 0x10139000 macro
|
| H A D | rk1808_common.h | 28 #define GICD_BASE 0xff100000 macro
|
| H A D | meson-gxbb-common.h | 25 #define GICD_BASE 0xc4301000 macro
|
| H A D | rk3288_common.h | 31 #define GICD_BASE 0xffc01000 macro
|
| H A D | rk3399_common.h | 30 #define GICD_BASE 0xFEE00000 macro
|
| H A D | px30_common.h | 32 #define GICD_BASE 0xff131000 macro
|
| H A D | salvator-x.h | 48 #define GICD_BASE 0xF1010000 macro
|
| H A D | rk3562_common.h | 36 #define GICD_BASE 0xfe901000 macro
|
| H A D | rk3506_common.h | 33 #define GICD_BASE 0xff581000 macro
|
| H A D | rk3308_common.h | 37 #define GICD_BASE 0xff581000 macro
|
| H A D | hikey.h | 47 #define GICD_BASE 0xf6801000 macro
|
| H A D | thunderx_88xx.h | 43 #define GICD_BASE (0x801000000000) macro
|
| H A D | rv1126_common.h | 35 #define GICD_BASE 0xfeff1000 macro
|
| H A D | rk3576_common.h | 39 #define GICD_BASE 0x2a701000 macro
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/sunxi/ |
| H A D | psci.c | 27 #define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET) macro
284 writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); in psci_cpu_off()
297 clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15)); in psci_arch_init()
300 writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15); in psci_arch_init()
|
| /rk3399_rockchip-uboot/arch/arm/mach-snapdragon/include/mach/ |
| H A D | sysmap-apq8016.h | 11 #define GICD_BASE 0x0b000000 macro
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra186/ |
| H A D | tegra.h | 10 #define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */ macro
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra210/ |
| H A D | tegra.h | 11 #define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ macro
|