rockchip: rk3288: Locate fdt at 0x08100000

Before this patch, the FDT(Flattened Device Tree) blob is located at
0x08300000, and the following 13MB from 0x08400000 is used as OPTEE
memory which will

rockchip: rk3288: Locate fdt at 0x08100000

Before this patch, the FDT(Flattened Device Tree) blob is located at
0x08300000, and the following 13MB from 0x08400000 is used as OPTEE
memory which will be set to be secure.

The kernel will map at least 2MB (4MB if LPAE=y) for the FDT blob, make
the 0x08400000 be mapped to the kernel, cpu or device access them will fail.

When LPAE is enabled, 0x08100000 is round down to 0x08000000 and then
map 4MB size which is not over 0x08400000, so 0x08100000 is also safe.

Such as
[ 106.766128] 8<--- cut here ---
[ 106.769224] Unhandled fault: imprecise external abort (0x406) at 0xb5fde000
[ 106.776209] pgd = 94a412ca
[ 106.778936] [b5fde000] *pgd=043c3835, *pte=703a175f, *ppte=703a1c7f

Change-Id: Ia4efb0dad695996e3f825805d4c6e336a7e4d1a3
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

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include: rockchip: remove CONFIG_SUPPORT_EMMC_RPMB

The macro is default selected.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I6966779ca63119cd210cd04268f2481ef795fcbf

Merge branch 'next-dev' into thunder-boot

configs: rk3288: remove initrd/fdt high

We place them at the address lower than 256MB, remove this
in order to enable relocation skip by android_image_separate().

Signed-off-by: Joseph Chen <chenjh

configs: rk3288: remove initrd/fdt high

We place them at the address lower than 256MB, remove this
in order to enable relocation skip by android_image_separate().

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ic1d5c949572902122547aad830761743dd7ecb05

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Merge branch 'next-dev' into thunder-boot

rockchip: update CONFIG_SPL_MAX_SIZE to 0x40000

We are using DRAM offset 0~0x40000 as SPL text size, Note that BSS,
STACK and MALLOC may using separate space.

Change-Id: I1d9128b339140569e427fad44d

rockchip: update CONFIG_SPL_MAX_SIZE to 0x40000

We are using DRAM offset 0~0x40000 as SPL text size, Note that BSS,
STACK and MALLOC may using separate space.

Change-Id: I1d9128b339140569e427fad44dc0a2f3058deaf0
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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configs: rk3288: update malloc size to 32MB

Since AVB use sysmem alloc, we can decrease malloc size.

Change-Id: Ic5a2df1fbfec0e6d94f9904042db8961aa0abf4d
Signed-off-by: Joseph Chen <chenjh@rock-chi

configs: rk3288: update malloc size to 32MB

Since AVB use sysmem alloc, we can decrease malloc size.

Change-Id: Ic5a2df1fbfec0e6d94f9904042db8961aa0abf4d
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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UPSTREAM: Convert CONFIG_SPI to Kconfig

This converts the following to Kconfig:
CONFIG_SPI

This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the

UPSTREAM: Convert CONFIG_SPI to Kconfig

This converts the following to Kconfig:
CONFIG_SPI

This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the MPC8xx SPI driver. For now, just update
the CONFIG tests. This also involves reworking the default for
CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
reasonable default, as it does not cause any compile failures.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
(cherry picked from commit f1b1f77060beadbfe9f42a3be00019bd025afbd6)
Change-Id: Ie9f15ada869105eb407f41d4df7eecbaa916b940
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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UPSTREAM: Convert CONFIG_SF_DEFAULT_* to Kconfig

This converts the following to Kconfig:
CONFIG_SF_DEFAULT_BUS
CONFIG_SF_DEFAULT_CS
CONFIG_SF_DEFAULT_MODE
CONFIG_SF_DEFAULT_SPEED

I use move

UPSTREAM: Convert CONFIG_SF_DEFAULT_* to Kconfig

This converts the following to Kconfig:
CONFIG_SF_DEFAULT_BUS
CONFIG_SF_DEFAULT_CS
CONFIG_SF_DEFAULT_MODE
CONFIG_SF_DEFAULT_SPEED

I use moveconfig script and then manual check on generated u-boot.cfg
to solve the remaining issue.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I6aaaaf572649fd16925af9eb457ea19423372e60
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 14453fbfadc2f98ca35d6033140466c7a4b4947a)

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UPSTREAM: configs: Move CONFIG_SPI_FLASH into defconfigs

Completely move CONFIG_SPI_FLASH from remaining board header files to
defconfigs

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jag

UPSTREAM: configs: Move CONFIG_SPI_FLASH into defconfigs

Completely move CONFIG_SPI_FLASH from remaining board header files to
defconfigs

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Change-Id: Iab125975d8e45a953666dcc04c989da9ae9b7f93
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ea4805d6b26282451eee9c701a456225bcf7db85)

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configs: rk3288: enable avb for Android P

Change-Id: Ie06e7b32dcb49dbf385148a4b4414a2c5fefb36f
Signed-off-by: Chen Jinsen <kevin.chen@rock-chips.com>

include: rk3288: move fdt to 131M and ramdisk to 162M

It avoids fdt overlap with large boot.img/recovery.img, moving
fdt ahead of boot.img/recovery.img and moving ramdisk backward
is safer.

Change-

include: rk3288: move fdt to 131M and ramdisk to 162M

It avoids fdt overlap with large boot.img/recovery.img, moving
fdt ahead of boot.img/recovery.img and moving ramdisk backward
is safer.

Change-Id: I20248525ff5b99719bc9f7d0608723f67b728a7e
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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rockchip: rk3288: support TPL

rk3288 is going to use TPL+SPL as preloader.

Change-Id: I2c712564b7c3b4d7c826bda09135f7188b0abc22
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: update kernel default load address

The 32bit arm kernel load address should be end with 0x8000 for
non-compress Image.
The compress zImage is fine for different address because the
decompo

rockchip: update kernel default load address

The 32bit arm kernel load address should be end with 0x8000 for
non-compress Image.
The compress zImage is fine for different address because the
decomporess program will copy the Image to address end with 0x8000.

Change-Id: I26fc58f06324fd93dbaeeb39a0b81c81fde0fef5
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: rk3288: adjust U-Boot text base and init sp

- set text base to 2MB offset;
- set init sp to 4MB offset;

Change-Id: I9f250c3561cbe8c0b4ee1c9da625766f7306c2f2
Signed-off-by: Joseph Chen <ch

rockchip: rk3288: adjust U-Boot text base and init sp

- set text base to 2MB offset;
- set init sp to 4MB offset;

Change-Id: I9f250c3561cbe8c0b4ee1c9da625766f7306c2f2
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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config: rk3288: support android boot image

The boot.img will instead of the kernel.img and resource.img on linux
platform, so need to support android boot image in rk3288 uboot.

Change-Id: I6d7d42d

config: rk3288: support android boot image

The boot.img will instead of the kernel.img and resource.img on linux
platform, so need to support android boot image in rk3288 uboot.

Change-Id: I6d7d42d80026cad594e720e279b7213dd4adcadd
Signed-off-by: Lin Huang <hl@rock-chips.com>

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rockchip: config: add RKIMG_DET_BOOTDEV in soc headers

Change-Id: Ibf535e9b40b019888bdf8af1a660f8453d19db7d
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

rockchip/rk3288: modify CONFIG_BOOTCOMMAND

Support boot with resource.img kernel.img.

Change-Id: Ifbf4180322bde0c55f312e05c0eaebaed71406e5
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>

rockchip: update and move CONFIG_NR_DRAM_BANKS to common header

Most of SoCs have 2 banks after we enable OP-TEE,
for those still only have 1 bank soc, it's OK to use 2 bank
for the other one have s

rockchip: update and move CONFIG_NR_DRAM_BANKS to common header

Most of SoCs have 2 banks after we enable OP-TEE,
for those still only have 1 bank soc, it's OK to use 2 bank
for the other one have size 0 if not used.

Change-Id: Ifa0ee3e12960794c71398636e525ef853eae7870
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rockchip: rk3288: remove rockchip timer for sys timer

Use ARM arch timer instead

Change-Id: Id14b484aa49ee98f741463adc510403f244fd187
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

rockchip: enable SYS_NS16550 for all SoCs by default

All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Change-Id: I4be3a801bf5537b94ed0c100cb44f49d

rockchip: enable SYS_NS16550 for all SoCs by default

All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Change-Id: I4be3a801bf5537b94ed0c100cb44f49d78b8b15a
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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rk3288: vyasa: Add TPL support

Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.

So add TPL stage so-that adding new f

rk3288: vyasa: Add TPL support

Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.

So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc

Change-Id: I8e570e6a552b37dbe7e3c9cc879f70ff64f2354e
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(update tpl text base, add memcpy/memset back)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 532cb7f5ada0cc3779c33606d760ec99f6aa847a)

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usb: gadget: force rockchip vid and pid for rockusb

This change amend USB VID & PID to Rockchip for rockusb.

Change-Id: I3c94e442cc0190d2d3f13424470dd2d84af55eb0
Signed-off-by: Frank Wang <frank.wa

usb: gadget: force rockchip vid and pid for rockusb

This change amend USB VID & PID to Rockchip for rockusb.

Change-Id: I3c94e442cc0190d2d3f13424470dd2d84af55eb0
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>

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UPSTREAM: rockchip: rk3288: use aligned address for SPL_TEXT_BASE

After we use boot0 hook, we can use offset '000' instead of '004' as
SPL_TEXT_BASE.

Change-Id: Ic29be8ee07382b641865281041e25aa8a8a

UPSTREAM: rockchip: rk3288: use aligned address for SPL_TEXT_BASE

After we use boot0 hook, we can use offset '000' instead of '004' as
SPL_TEXT_BASE.

Change-Id: Ic29be8ee07382b641865281041e25aa8a8a61333
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[Updated tag in commit summary:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

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rockchip: config: use common CONFIG_ENV_SIZE for all SoCs

All Rockchip SoCs use 32KB as CONFIG_ENV_SIZE.

Change-Id: I4e7bb94be70ece871fa339feb90a591f889e833d
Signed-off-by: Kever Yang <kever.yang@r

rockchip: config: use common CONFIG_ENV_SIZE for all SoCs

All Rockchip SoCs use 32KB as CONFIG_ENV_SIZE.

Change-Id: I4e7bb94be70ece871fa339feb90a591f889e833d
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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