1581183deSNobuhiro Iwamatsu/* 2581183deSNobuhiro Iwamatsu * arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S 3581183deSNobuhiro Iwamatsu * This file is lowlevel initialize routine. 4581183deSNobuhiro Iwamatsu * 5581183deSNobuhiro Iwamatsu * (C) Copyright 2015 Renesas Electronics Corporation 6581183deSNobuhiro Iwamatsu * 7581183deSNobuhiro Iwamatsu * This file is based on the arch/arm/cpu/armv8/start.S 8581183deSNobuhiro Iwamatsu * 9581183deSNobuhiro Iwamatsu * (C) Copyright 2013 10581183deSNobuhiro Iwamatsu * David Feng <fenghua@phytium.com.cn> 11581183deSNobuhiro Iwamatsu * 12581183deSNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0+ 13581183deSNobuhiro Iwamatsu */ 14581183deSNobuhiro Iwamatsu 15581183deSNobuhiro Iwamatsu#include <asm-offsets.h> 16581183deSNobuhiro Iwamatsu#include <config.h> 17581183deSNobuhiro Iwamatsu#include <linux/linkage.h> 18581183deSNobuhiro Iwamatsu#include <asm/macro.h> 19581183deSNobuhiro Iwamatsu 20581183deSNobuhiro IwamatsuENTRY(lowlevel_init) 21581183deSNobuhiro Iwamatsu mov x29, lr /* Save LR */ 22581183deSNobuhiro Iwamatsu 23581183deSNobuhiro Iwamatsu#ifndef CONFIG_ARMV8_MULTIENTRY 24581183deSNobuhiro Iwamatsu /* 25581183deSNobuhiro Iwamatsu * For single-entry systems the lowlevel init is very simple. 26581183deSNobuhiro Iwamatsu */ 27581183deSNobuhiro Iwamatsu ldr x0, =GICD_BASE 28581183deSNobuhiro Iwamatsu bl gic_init_secure 29581183deSNobuhiro Iwamatsu 30581183deSNobuhiro Iwamatsu#else /* CONFIG_ARMV8_MULTIENTRY is set */ 31581183deSNobuhiro Iwamatsu 32581183deSNobuhiro Iwamatsu#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 33581183deSNobuhiro Iwamatsu branch_if_slave x0, 1f 34581183deSNobuhiro Iwamatsu ldr x0, =GICD_BASE 35581183deSNobuhiro Iwamatsu bl gic_init_secure 36581183deSNobuhiro Iwamatsu1: 37581183deSNobuhiro Iwamatsu#if defined(CONFIG_GICV3) 38581183deSNobuhiro Iwamatsu ldr x0, =GICR_BASE 39581183deSNobuhiro Iwamatsu bl gic_init_secure_percpu 40581183deSNobuhiro Iwamatsu#elif defined(CONFIG_GICV2) 41581183deSNobuhiro Iwamatsu ldr x0, =GICD_BASE 42581183deSNobuhiro Iwamatsu ldr x1, =GICC_BASE 43581183deSNobuhiro Iwamatsu bl gic_init_secure_percpu 44581183deSNobuhiro Iwamatsu#endif 45581183deSNobuhiro Iwamatsu#endif 46581183deSNobuhiro Iwamatsu 47581183deSNobuhiro Iwamatsu branch_if_master x0, x1, 2f 48581183deSNobuhiro Iwamatsu 49581183deSNobuhiro Iwamatsu /* 50581183deSNobuhiro Iwamatsu * Slave should wait for master clearing spin table. 51581183deSNobuhiro Iwamatsu * This sync prevent salves observing incorrect 52581183deSNobuhiro Iwamatsu * value of spin table and jumping to wrong place. 53581183deSNobuhiro Iwamatsu */ 54581183deSNobuhiro Iwamatsu#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 55581183deSNobuhiro Iwamatsu#ifdef CONFIG_GICV2 56581183deSNobuhiro Iwamatsu ldr x0, =GICC_BASE 57581183deSNobuhiro Iwamatsu#endif 58581183deSNobuhiro Iwamatsu bl gic_wait_for_interrupt 59581183deSNobuhiro Iwamatsu#endif 60581183deSNobuhiro Iwamatsu 61581183deSNobuhiro Iwamatsu /* 62581183deSNobuhiro Iwamatsu * All slaves will enter EL2 and optionally EL1. 63581183deSNobuhiro Iwamatsu */ 64*7c5e1febSAlison Wang adr x4, lowlevel_in_el2 65*7c5e1febSAlison Wang ldr x5, =ES_TO_AARCH64 66581183deSNobuhiro Iwamatsu bl armv8_switch_to_el2 67581183deSNobuhiro Iwamatsu 68ec6617c3SAlison Wanglowlevel_in_el2: 69ec6617c3SAlison Wang#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 70*7c5e1febSAlison Wang adr x4, lowlevel_in_el1 71*7c5e1febSAlison Wang ldr x5, =ES_TO_AARCH64 72ec6617c3SAlison Wang bl armv8_switch_to_el1 73ec6617c3SAlison Wang 74ec6617c3SAlison Wanglowlevel_in_el1: 75ec6617c3SAlison Wang#endif 76581183deSNobuhiro Iwamatsu#endif /* CONFIG_ARMV8_MULTIENTRY */ 77581183deSNobuhiro Iwamatsu 78581183deSNobuhiro Iwamatsu bl s_init 79581183deSNobuhiro Iwamatsu 80581183deSNobuhiro Iwamatsu2: 81581183deSNobuhiro Iwamatsu mov lr, x29 /* Restore LR */ 82581183deSNobuhiro Iwamatsu ret 83581183deSNobuhiro IwamatsuENDPROC(lowlevel_init) 84