1b8fa3d2aSJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2b8fa3d2aSJoseph Chen /* 3b8fa3d2aSJoseph Chen * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4b8fa3d2aSJoseph Chen * 5b8fa3d2aSJoseph Chen */ 6b8fa3d2aSJoseph Chen 7b8fa3d2aSJoseph Chen #ifndef __CONFIG_RK1808_COMMON_H 8b8fa3d2aSJoseph Chen #define __CONFIG_RK1808_COMMON_H 9b8fa3d2aSJoseph Chen 10b8fa3d2aSJoseph Chen #include "rockchip-common.h" 11b8fa3d2aSJoseph Chen 12b4761549SJason Zhu #define CONFIG_SPL_FRAMEWORK 13b4761549SJason Zhu #define CONFIG_SPL_TEXT_BASE 0x00000000 14b4761549SJason Zhu #define CONFIG_SPL_MAX_SIZE 0x00020000 15b4761549SJason Zhu #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16b4761549SJason Zhu #define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 17b4761549SJason Zhu #define CONFIG_SPL_STACK 0x03fe0000 18b4761549SJason Zhu 19b8fa3d2aSJoseph Chen #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20b8fa3d2aSJoseph Chen #define CONFIG_SYS_CBSIZE 1024 21b8fa3d2aSJoseph Chen #define CONFIG_SKIP_LOWLEVEL_INIT 22225168aaSJoseph Chen #define CONFIG_SYS_TEXT_BASE 0x00600000 23225168aaSJoseph Chen #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 24b8fa3d2aSJoseph Chen #define CONFIG_SYS_LOAD_ADDR 0x00800800 25b8fa3d2aSJoseph Chen #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 26b8fa3d2aSJoseph Chen #define COUNTER_FREQUENCY 24000000 27b8fa3d2aSJoseph Chen 28b8fa3d2aSJoseph Chen #define GICD_BASE 0xff100000 29b8fa3d2aSJoseph Chen #define GICR_BASE 0xff140000 30b8fa3d2aSJoseph Chen #define GICC_BASE 0xff300000 31b8fa3d2aSJoseph Chen 32b8fa3d2aSJoseph Chen /* MMC/SD IP block */ 33b8fa3d2aSJoseph Chen #define CONFIG_BOUNCE_BUFFER 34b8fa3d2aSJoseph Chen 356b5189e7SJason Zhu /* Nand */ 366b5189e7SJason Zhu #define CONFIG_SYS_MAX_NAND_DEVICE 1 376b5189e7SJason Zhu #define CONFIG_SYS_NAND_ONFI_DETECTION 386b5189e7SJason Zhu #define CONFIG_SYS_NAND_PAGE_SIZE 2048 396b5189e7SJason Zhu #define CONFIG_SYS_NAND_PAGE_COUNT 64 406b5189e7SJason Zhu #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 416b5189e7SJason Zhu #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 426b5189e7SJason Zhu 43b8fa3d2aSJoseph Chen #define CONFIG_SYS_SDRAM_BASE 0 44c664c887SJoseph Chen #define SDRAM_MAX_SIZE 0xf8000000 45b8fa3d2aSJoseph Chen #define SDRAM_BANK_SIZE (2UL << 30) 46b8fa3d2aSJoseph Chen #define CONFIG_PREBOOT 47b8fa3d2aSJoseph Chen 48b8fa3d2aSJoseph Chen #ifndef CONFIG_SPL_BUILD 49b8fa3d2aSJoseph Chen /* usb mass storage */ 50dd620b63SWilliam Wu #define CONFIG_USB_FUNCTION_MASS_STORAGE 51dd620b63SWilliam Wu #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 52b8fa3d2aSJoseph Chen 53b8fa3d2aSJoseph Chen #define ENV_MEM_LAYOUT_SETTINGS \ 54b8fa3d2aSJoseph Chen "scriptaddr=0x00500000\0" \ 55b8fa3d2aSJoseph Chen "pxefile_addr_r=0x00600000\0" \ 56b8fa3d2aSJoseph Chen "fdt_addr_r=0x01f00000\0" \ 57*49e18ddbSJoseph Chen "kernel_addr_no_low_bl32_r=0x00280000\0" \ 58caf555d0SJoseph Chen "kernel_addr_r=0x00680000\0" \ 591dfe3932SJoseph Chen "kernel_addr_c=0x04080000\0" \ 60b8fa3d2aSJoseph Chen "ramdisk_addr_r=0x0a200000\0" 61b8fa3d2aSJoseph Chen 62b8fa3d2aSJoseph Chen #include <config_distro_bootcmd.h> 63bf6219b0SJoseph Chen 64b8fa3d2aSJoseph Chen #define CONFIG_EXTRA_ENV_SETTINGS \ 65b8fa3d2aSJoseph Chen ENV_MEM_LAYOUT_SETTINGS \ 66b8fa3d2aSJoseph Chen "partitions=" PARTS_DEFAULT \ 67b8fa3d2aSJoseph Chen ROCKCHIP_DEVICE_SETTINGS \ 68b8fa3d2aSJoseph Chen RKIMG_DET_BOOTDEV \ 69b8fa3d2aSJoseph Chen BOOTENV 70b8fa3d2aSJoseph Chen #endif 71b8fa3d2aSJoseph Chen 72b8fa3d2aSJoseph Chen #endif /* __CONFIG_RK1808_COMMON_H */ 73