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Searched refs:CLK_PWM0_SEL_SHIFT (Results 1 – 12 of 12) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rv1103b.h219 CLK_PWM0_SEL_SHIFT = 12, enumerator
220 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
H A Dcru_rv1106.h275 CLK_PWM0_SEL_SHIFT = 0, enumerator
276 CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
H A Dcru_rv1126.h187 CLK_PWM0_SEL_SHIFT = 7, enumerator
188 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
H A Dcru_rk3528.h200 CLK_PWM0_SEL_SHIFT = 6, enumerator
201 CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
H A Dcru_rv1126b.h326 CLK_PWM0_SEL_SHIFT = 8, enumerator
327 CLK_PWM0_SEL_MASK = 0x1 << CLK_PWM0_SEL_SHIFT,
H A Dcru_rk3568.h154 CLK_PWM0_SEL_SHIFT = 7, enumerator
155 CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1103b.c487 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1103b_pwm_get_clk()
527 src_clk << CLK_PWM0_SEL_SHIFT); in rv1103b_pwm_set_clk()
H A Dclk_rv1106.c629 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1106_pwm_get_clk()
672 src_clk << CLK_PWM0_SEL_SHIFT); in rv1106_pwm_set_clk()
H A Dclk_rk3568.c292 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rk3568_pwm_get_pmuclk()
318 CLK_PWM0_SEL_SHIFT) | in rk3568_pwm_set_pmuclk()
319 0 << CLK_PWM0_SEL_SHIFT); in rk3568_pwm_set_pmuclk()
325 (CLK_PWM0_SEL_PPLL << CLK_PWM0_SEL_SHIFT) | in rk3568_pwm_set_pmuclk()
H A Dclk_rv1126.c269 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1126_pwm_get_pmuclk()
299 CLK_PWM0_SEL_XIN24M << CLK_PWM0_SEL_SHIFT); in rv1126_pwm_set_pmuclk()
310 CLK_PWM0_SEL_GPLL << CLK_PWM0_SEL_SHIFT); in rv1126_pwm_set_pmuclk()
H A Dclk_rk3528.c785 shift = CLK_PWM0_SEL_SHIFT; in rk3528_pwm_get_clk()
827 shift = CLK_PWM0_SEL_SHIFT; in rk3528_pwm_set_clk()
H A Dclk_rv1126b.c590 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; in rv1126b_pwm_get_clk()
640 src_clk << CLK_PWM0_SEL_SHIFT); in rv1126b_pwm_set_clk()