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/rk3399_ARM-atf/include/arch/aarch32/
H A Del3_common_macros.S34 ldcopr r0, SCTLR
35 orr r0, r0, r1
36 stcopr r0, SCTLR
46 ldr r0, =(SCR_RESET_VAL | SCR_SIF_BIT)
47 stcopr r0, SCR
74 ldcopr r0, NSACR
75 and r0, r0, #NSACR_IMP_DEF_MASK
76 orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
81 orr r0, r0, #NSTRCDIS_BIT
83 stcopr r0, NSACR
[all …]
/rk3399_ARM-atf/lib/cpus/aarch32/
H A Dcortex_a57.S19 ldcopr16 r0, r1, CORTEX_A57_ECTLR
20 bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
21 stcopr16 r0, r1, CORTEX_A57_ECTLR
31 ldcopr16 r0, r1, CORTEX_A57_ECTLR
32 orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
33 bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \
35 stcopr16 r0, r1, CORTEX_A57_ECTLR
46 mov r0, #1
47 stcopr r0, DBGOSDLR
53 mov r0, #0
[all …]
H A Dcortex_a17.S15 ldcopr r0, SCTLR
16 tst r0, #SCTLR_C_BIT
22 ldcopr r0, ACTLR
23 bic r0, #CORTEX_A17_ACTLR_SMP_BIT
24 stcopr r0, ACTLR
31 ldcopr r0, ACTLR
32 orr r0, #CORTEX_A17_ACTLR_SMP_BIT
33 stcopr r0, ACTLR
52 cmp r0, #ERRATA_NOT_APPLIES
54 ldcopr r0, CORTEX_A17_IMP_DEF_REG1
[all …]
H A Dcortex_a72.S18 ldcopr16 r0, r1, CORTEX_A72_ECTLR
19 orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
20 bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \
22 stcopr16 r0, r1, CORTEX_A72_ECTLR
32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
33 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR
46 ldcopr16 r0, r1, CORTEX_A72_ECTLR
47 bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT
48 stcopr16 r0, r1, CORTEX_A72_ECTLR
[all …]
H A Dcortex_a15.S21 ldcopr r0, SCTLR
22 tst r0, #SCTLR_C_BIT
28 ldcopr r0, ACTLR
29 bic r0, #CORTEX_A15_ACTLR_SMP_BIT
30 stcopr r0, ACTLR
36 mov r0, #0
37 stcopr r0, TLBIMVA
44 ldcopr r0, ACTLR
45 orr r0, #CORTEX_A15_ACTLR_SMP_BIT
46 stcopr r0, ACTLR
[all …]
H A Dcortex_a53.S24 ldcopr16 r0, r1, CORTEX_A53_ECTLR
25 bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
26 stcopr16 r0, r1, CORTEX_A53_ECTLR
43 mov r0, #ERRATA_APPLIES
60 mov r0, #ERRATA_APPLIES
81 cmp r0, #ERRATA_NOT_APPLIES
83 ldcopr r0, CORTEX_A53_L2ACTLR
84 bic r0, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
85 orr r0, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
86 stcopr r0, CORTEX_A53_L2ACTLR
[all …]
H A Dcortex_a32.S20 ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
21 bic r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
22 stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
38 ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
39 orr r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
40 stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
56 ldcopr r0, SCTLR
57 tst r0, #SCTLR_C_BIT
65 mov r0, #DC_OP_CISW
87 ldcopr r0, SCTLR
[all …]
H A Dcortex_a9.S15 ldcopr r0, SCTLR
16 tst r0, #SCTLR_C_BIT
22 ldcopr r0, ACTLR
23 bic r0, #CORTEX_A9_ACTLR_SMP_BIT
24 stcopr r0, ACTLR
31 ldcopr r0, ACTLR
32 orr r0, #CORTEX_A9_ACTLR_SMP_BIT
33 stcopr r0, ACTLR
40 mov r0, #ERRATA_APPLIES
42 mov r0, #ERRATA_MISSING
[all …]
H A Dcortex_a12.S15 ldcopr r0, SCTLR
16 tst r0, #SCTLR_C_BIT
22 ldcopr r0, ACTLR
23 bic r0, #CORTEX_A12_ACTLR_SMP_BIT
24 stcopr r0, ACTLR
31 ldcopr r0, ACTLR
32 orr r0, #CORTEX_A12_ACTLR_SMP_BIT
33 stcopr r0, ACTLR
48 mov r0, #DC_OP_CISW
62 mov r0, #DC_OP_CISW
[all …]
/rk3399_ARM-atf/drivers/arm/pl011/aarch32/
H A Dpl011_console.S42 cmp r0, #0
51 ldr r3, [r0, #UARTCR]
53 str r3, [r0, #UARTCR]
58 push {r0,r3}
59 softudiv r0,r1,r2,r3
60 mov r2, r0
61 pop {r0,r3}
68 str r1, [r0, #UARTIBRD]
72 str r1, [r0, #UARTFBRD]
74 str r1, [r0, #UARTLCR_H]
[all …]
/rk3399_ARM-atf/plat/arm/css/common/aarch32/
H A Dcss_helpers.S44 ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
45 ldr r0, [r0]
58 and r1, r0, #MPIDR_CPU_MASK
59 and r0, r0, #MPIDR_CLUSTER_MASK
60 eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
61 add r0, r1, r0, LSR #6
76 mov r4, r0
80 cmp r0, r1
82 cmp r0, r4
83 moveq r0, #1
[all …]
/rk3399_ARM-atf/plat/arm/board/a5ds/aarch32/
H A Da5ds_helpers.S27 lsl r0, r0, #A5DS_HOLD_ENTRY_SHIFT
31 str r3, [r2, r0]
36 ldr r1, [r2, r0]
39 mov_imm r0, A5DS_TRUSTED_MAILBOX_BASE
40 ldr r1, [r0]
57 mov r0, #0
70 ldcopr r0, MPIDR
72 and r0, r1
73 cmp r0, #0
74 moveq r0, #1
[all …]
/rk3399_ARM-atf/plat/qemu/common/aarch32/
H A Dplat_helpers.S25 ldcopr r0, MPIDR
34 and r1, r0, #MPIDR_CPU_MASK
35 and r0, r0, #MPIDR_CLUSTER_MASK
36 add r0, r1, r0, LSR #6
48 ldcopr r0, MPIDR
50 and r0, r1
51 cmp r0, #QEMU_PRIMARY_CPU
52 moveq r0, #1
53 movne r0, #0
69 lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
[all …]
/rk3399_ARM-atf/drivers/ti/uart/aarch32/
H A D16550_console.S42 cmp r0, #0
57 ldr r3, [r0, #UARTLCR]
59 str r3, [r0, #UARTLCR] /* enable DLL, DLLM programming */
60 str r1, [r0, #UARTDLL] /* program DLL */
61 str r2, [r0, #UARTDLLM] /* program DLLM */
64 str r3, [r0, #UARTLCR] /* disable DLL, DLLM programming */
68 str r3, [r0, #UARTLCR]
71 str r3, [r0, #UARTIER]
74 str r3, [r0, #UARTMDR1]
78 str r3, [r0, #UARTFCR]
[all …]
/rk3399_ARM-atf/bl2/aarch32/
H A Dbl2_entrypoint.S32 mov r8, r0
41 ldr r0, =bl2_vector_table
42 stcopr r0, VBAR
49 ldcopr r0, SCTLR
50 orr r0, r0, #SCTLR_I_BIT
51 bic r0, r0, #SCTLR_DSSBS_BIT
52 stcopr r0, SCTLR
71 ldr r0, =__RW_START__
73 sub r1, r1, r0
82 ldr r0, =__BSS_START__
[all …]
/rk3399_ARM-atf/bl32/sp_min/aarch32/
H A Dentrypoint.S69 mov r9, r0
117 mov r0, r9
133 ldr r0, =__DATA_START__
135 sub r1, r1, r0
138 ldr r0, =__BSS_START__
140 sub r1, r1, r0
143 ldr r0, =__PER_CPU_START__
145 sub r1, r1, r0
169 strd r0, r1, [sp, #SMC_CTX_GPREG_R0]
170 ldcopr16 r0, r1, CNTPCT_64
[all …]
/rk3399_ARM-atf/plat/arm/board/fvp/aarch32/
H A Dfvp_helpers.S64 mov r0, #0
74 ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
75 ldr r0, [r0]
76 cmp r0, #0
97 ldcopr r0, MPIDR
99 and r0, r1
100 cmp r0, #FVP_PRIMARY_CPU
101 moveq r0, #1
102 movne r0, #0
122 mov r3, r0
[all …]
/rk3399_ARM-atf/bl2u/aarch32/
H A Dbl2u_entrypoint.S40 ldr r0, =bl2u_vector_table
41 stcopr r0, VBAR
48 ldcopr r0, SCTLR
49 orr r0, r0, #SCTLR_I_BIT
50 bic r0, r0, #SCTLR_DSSBS_BIT
51 stcopr r0, SCTLR
70 ldr r0, =__RW_START__
72 sub r1, r1, r0
81 ldr r0, =__BSS_START__
83 sub r1, r1, r0
[all …]
/rk3399_ARM-atf/drivers/st/uart/aarch32/
H A Dstm32_console.S46 cmp r0, #0
55 ldr r3, [r0, #USART_CR1]
66 ldr r3, [r0, #USART_CR1]
68 str r3, [r0, #USART_CR1]
71 str r3, [r0, #USART_CR1]
72 ldr r3, [r0, #USART_CR2]
74 str r3, [r0, #USART_CR2]
90 ldr r1, [r0, #USART_CR1]
92 str r1, [r0, #USART_CR1]
94 str r3, [r0, #USART_BRR]
[all …]
/rk3399_ARM-atf/plat/arm/board/juno/aarch32/
H A Djuno_helpers.S31 cmp r0, #\_revision
54 mov r0, #(0xf << EVNTI_SHIFT)
55 orr r0, r0, #EVNTEN_BIT
56 stcopr r0, CNTKCTL
68 mov r0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
70 stcopr r0, CORTEX_A57_L2CTLR
105 mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
106 stcopr r0, CORTEX_A57_L2CTLR
139 mov r0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
141 stcopr r0, CORTEX_A72_L2CTLR
[all …]
/rk3399_ARM-atf/plat/rockchip/common/aarch32/
H A Dplat_helpers.S38 ldcopr r0, MPIDR
39 and r1, r0, #MPIDR_CPU_MASK
41 and r0, r0, #PLAT_RK_MPIDR_CLUSTER_MASK
43 and r0, r0, #MPIDR_CLUSTER_MASK
45 add r0, r1, r0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
65 ldcopr r0, MPIDR
71 and r0, r1
72 cmp r0, #PLAT_RK_PRIMARY_CPU
73 moveq r0, #1
74 movne r0, #0
[all …]
/rk3399_ARM-atf/common/aarch32/
H A Ddebug.S50 udiv r0, r4, r5 /* Get the quotient */
51 mls r4, r0, r5, r4 /* Find the remainder */
52 add r0, r0, #ASCII_OFFSET_NUM /* Convert to ascii */
76 mov r5, r0
83 cmp r0, #0
123 ldrb r0, [r4], #0x1
124 cmp r0, #0
145 lsr r0, r4, r5
146 and r0, r0, #0xf
147 cmp r0, #0xa
[all …]
/rk3399_ARM-atf/drivers/arm/css/sds/aarch32/
H A Dsds_helpers.S22 ldr r0, =PLAT_ARM_SDS_MEM_BASE
24 ldr r1, [r0]
35 add r0, r0, #SDS_REGION_DESC_SIZE
40 ldrh r2, [r0]
45 ldr r0, [r0,#(SDS_HEADER_SIZE + SDS_AP_CPU_INFO_PRIMARY_CPUID_OFFSET)]
54 ldr r2, [r0,#4]
59 add r0, r0, r2
62 mov r0, #0xffffffff
/rk3399_ARM-atf/lib/psci/aarch32/
H A Dpsci_helpers.S37 mov r4, r0
39 sub r1, r0, r1
40 mov r0, sp
49 sub r0, r4, #PLATFORM_STACK_SIZE
50 sub r1, sp, r0
84 sub r1, r0, r1
85 mov r0, sp
92 ldcopr r0, SCTLR
93 orr r0, r0, #SCTLR_C_BIT
94 stcopr r0, SCTLR
/rk3399_ARM-atf/bl1/aarch32/
H A Dbl1_exceptions.S34 cmp lr, r0
52 mov r0, r1
61 mov r0, r8
64 stcopr r0, TLBIALL
82 ldm r8, {r0, r1, r2, r3}
105 ldr r0, [r6, #SMC_CTX_SCR]
106 and r7, r0, #SCR_NS_BIT /* flags */
109 bic r0, #SCR_NS_BIT
110 stcopr r0, SCR
118 mov r0, #DISABLE_DCACHE
[all …]

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