1e3148c2bSEtienne Carriere/* 2*3fb52e41SRyan Everett * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3e3148c2bSEtienne Carriere * 4e3148c2bSEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 5e3148c2bSEtienne Carriere */ 6e3148c2bSEtienne Carriere 7e3148c2bSEtienne Carriere#include <arch.h> 8e3148c2bSEtienne Carriere#include <asm_macros.S> 9e3148c2bSEtienne Carriere#include <assert_macros.S> 10e3148c2bSEtienne Carriere#include <cortex_a9.h> 11e3148c2bSEtienne Carriere#include <cpu_macros.S> 12e3148c2bSEtienne Carriere 13e3148c2bSEtienne Carriere .macro assert_cache_enabled 14e3148c2bSEtienne Carriere#if ENABLE_ASSERTIONS 15e3148c2bSEtienne Carriere ldcopr r0, SCTLR 16e3148c2bSEtienne Carriere tst r0, #SCTLR_C_BIT 17e3148c2bSEtienne Carriere ASM_ASSERT(eq) 18e3148c2bSEtienne Carriere#endif 19e3148c2bSEtienne Carriere .endm 20e3148c2bSEtienne Carriere 21e3148c2bSEtienne Carrierefunc cortex_a9_disable_smp 22e3148c2bSEtienne Carriere ldcopr r0, ACTLR 23e3148c2bSEtienne Carriere bic r0, #CORTEX_A9_ACTLR_SMP_BIT 24e3148c2bSEtienne Carriere stcopr r0, ACTLR 25e3148c2bSEtienne Carriere isb 26e3148c2bSEtienne Carriere dsb sy 27e3148c2bSEtienne Carriere bx lr 28e3148c2bSEtienne Carriereendfunc cortex_a9_disable_smp 29e3148c2bSEtienne Carriere 30e3148c2bSEtienne Carrierefunc cortex_a9_enable_smp 31e3148c2bSEtienne Carriere ldcopr r0, ACTLR 32e3148c2bSEtienne Carriere orr r0, #CORTEX_A9_ACTLR_SMP_BIT 33e3148c2bSEtienne Carriere stcopr r0, ACTLR 34e3148c2bSEtienne Carriere isb 35e3148c2bSEtienne Carriere bx lr 36e3148c2bSEtienne Carriereendfunc cortex_a9_enable_smp 37e3148c2bSEtienne Carriere 383ca54cb4SGovindraj Rajafunc check_errata_794073 39dd4cf2c7SJoel Hutton#if ERRATA_A9_794073 40dd4cf2c7SJoel Hutton mov r0, #ERRATA_APPLIES 41dd4cf2c7SJoel Hutton#else 42dd4cf2c7SJoel Hutton mov r0, #ERRATA_MISSING 43dd4cf2c7SJoel Hutton#endif 44dd4cf2c7SJoel Hutton bx lr 453ca54cb4SGovindraj Rajaendfunc check_errata_794073 463ca54cb4SGovindraj Raja 473ca54cb4SGovindraj Rajaadd_erratum_entry cortex_a9, ERRATUM(794073), ERRATA_A9_794073 48dd4cf2c7SJoel Hutton 49e4b34efaSDimitris Papastamosfunc check_errata_cve_2017_5715 50e4b34efaSDimitris Papastamos#if WORKAROUND_CVE_2017_5715 51e4b34efaSDimitris Papastamos mov r0, #ERRATA_APPLIES 52e4b34efaSDimitris Papastamos#else 53e4b34efaSDimitris Papastamos mov r0, #ERRATA_MISSING 54e4b34efaSDimitris Papastamos#endif 55e4b34efaSDimitris Papastamos bx lr 56e4b34efaSDimitris Papastamosendfunc check_errata_cve_2017_5715 57e4b34efaSDimitris Papastamos 583ca54cb4SGovindraj Rajaadd_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 59e4b34efaSDimitris Papastamos 60e3148c2bSEtienne Carrierefunc cortex_a9_reset_func 61e4b34efaSDimitris Papastamos#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 62bcb3ea92SHarrison Mutai ldr r0, =wa_cve_2017_5715_bpiall_vbar 63e4b34efaSDimitris Papastamos stcopr r0, VBAR 64e4b34efaSDimitris Papastamos stcopr r0, MVBAR 65e4b34efaSDimitris Papastamos /* isb will be applied in the course of the reset func */ 66e4b34efaSDimitris Papastamos#endif 67e3148c2bSEtienne Carriere b cortex_a9_enable_smp 68e3148c2bSEtienne Carriereendfunc cortex_a9_reset_func 69e3148c2bSEtienne Carriere 70e3148c2bSEtienne Carrierefunc cortex_a9_core_pwr_dwn 71e3148c2bSEtienne Carriere push {r12, lr} 72e3148c2bSEtienne Carriere 73e3148c2bSEtienne Carriere assert_cache_enabled 74e3148c2bSEtienne Carriere 75e3148c2bSEtienne Carriere /* Flush L1 cache */ 76e3148c2bSEtienne Carriere mov r0, #DC_OP_CISW 77e3148c2bSEtienne Carriere bl dcsw_op_level1 78e3148c2bSEtienne Carriere 79e3148c2bSEtienne Carriere /* Exit cluster coherency */ 80e3148c2bSEtienne Carriere pop {r12, lr} 81e3148c2bSEtienne Carriere b cortex_a9_disable_smp 82e3148c2bSEtienne Carriereendfunc cortex_a9_core_pwr_dwn 83e3148c2bSEtienne Carriere 84e3148c2bSEtienne Carrierefunc cortex_a9_cluster_pwr_dwn 85e3148c2bSEtienne Carriere push {r12, lr} 86e3148c2bSEtienne Carriere 87e3148c2bSEtienne Carriere assert_cache_enabled 88e3148c2bSEtienne Carriere 89e3148c2bSEtienne Carriere /* Flush L1 caches */ 90e3148c2bSEtienne Carriere mov r0, #DC_OP_CISW 91e3148c2bSEtienne Carriere bl dcsw_op_level1 92e3148c2bSEtienne Carriere 93e3148c2bSEtienne Carriere bl plat_disable_acp 94e3148c2bSEtienne Carriere 95e3148c2bSEtienne Carriere /* Exit cluster coherency */ 96e3148c2bSEtienne Carriere pop {r12, lr} 97e3148c2bSEtienne Carriere b cortex_a9_disable_smp 98e3148c2bSEtienne Carriereendfunc cortex_a9_cluster_pwr_dwn 99e3148c2bSEtienne Carriere 100e3148c2bSEtienne Carrieredeclare_cpu_ops cortex_a9, CORTEX_A9_MIDR, \ 101e3148c2bSEtienne Carriere cortex_a9_reset_func, \ 102e3148c2bSEtienne Carriere cortex_a9_core_pwr_dwn, \ 103e3148c2bSEtienne Carriere cortex_a9_cluster_pwr_dwn 104