Merge changes from topic "clean-up-errata-compatibility" into integration

* changes:
refactor(cpus): remove cpu specific errata funcs
refactor(cpus): directly invoke errata reporter

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.

Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "fix(cpus): flush L2 cache for Cortex-A7/12/15/17" into integration

fix(cpus): flush L2 cache for Cortex-A7/12/15/17

Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster

fix(cpus): flush L2 cache for Cortex-A7/12/15/17

Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.

Fix this by adding the L2 cache flush similar to cortex_a53.S.

Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge changes from topic "hm/errata-fw" into integration

* changes:
refactor(cpus): add Cortex-A17 errata framework information
fix(fvp): resolve broken workaround reference

refactor(cpus): add Cortex-A17 errata framework information

Change-Id: I19d096edf47c1a9f47e79e9bb95984ce2102fad4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

fix(fvp): resolve broken workaround reference

The workaround for CVE 2015-5715 was renamed many years ago, however,
Cortex-A17 and A9 didn't see this change.

Change-Id: I553c8b09543263bca2a34eaef67

fix(fvp): resolve broken workaround reference

The workaround for CVE 2015-5715 was renamed many years ago, however,
Cortex-A17 and A9 didn't see this change.

Change-Id: I553c8b09543263bca2a34eaef670af0424999cfe
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge pull request #1883 from ambroise-arm/av/a17-errata

Apply workarounds for errata of Cortex-A17

Cortex-A17: Implement workaround for errata 852423

Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Cortex-A17: Implement workaround for errata 852421

Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Merge pull request #1228 from dp-arm/dp/cve_2017_5715

Workarounds for CVE-2017-5715 on A9/A15 and A17 + serial console reporting

Workaround for CVE-2017-5715 for Cortex A9, A15 and A17

A per-cpu vbar is installed that implements the workaround by
invalidating the branch target buffer (BTB) directly in the case of A9
and A17 a

Workaround for CVE-2017-5715 for Cortex A9, A15 and A17

A per-cpu vbar is installed that implements the workaround by
invalidating the branch target buffer (BTB) directly in the case of A9
and A17 and indirectly by invalidating the icache in the case of A15.

For Cortex A57 and A72 there is currently no workaround implemented
when EL3 is in AArch32 mode so report it as missing.

For other vulnerable CPUs (e.g. Cortex A73 and Cortex A75), there are
no changes since there is currently no upstream AArch32 EL3 support
for these CPUs.

Change-Id: Ib42c6ef0b3c9ff2878a9e53839de497ff736258f
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Merge pull request #1145 from etienne-lms/rfc-armv7-2

Support ARMv7 architectures

ARMv7: introduce Cortex-A17

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>