16f249345SYatharth Kochar/* 218e279ebSSoby Mathew * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 36f249345SYatharth Kochar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56f249345SYatharth Kochar */ 6*234bc7f8SAntonio Nino Diaz 76f249345SYatharth Kochar#include <arch.h> 86f249345SYatharth Kochar#include <asm_macros.S> 96f249345SYatharth Kochar#include <cpu_macros.S> 10*234bc7f8SAntonio Nino Diaz#include <platform_def.h> 116f249345SYatharth Kochar 126f249345SYatharth Kochar .weak plat_secondary_cold_boot_setup 136f249345SYatharth Kochar .weak plat_get_my_entrypoint 146f249345SYatharth Kochar .globl css_calc_core_pos_swap_cluster 156f249345SYatharth Kochar .weak plat_is_my_cpu_primary 166f249345SYatharth Kochar 176f249345SYatharth Kochar /* --------------------------------------------------------------------- 186f249345SYatharth Kochar * void plat_secondary_cold_boot_setup(void); 196f249345SYatharth Kochar * In the normal boot flow, cold-booting secondary 206f249345SYatharth Kochar * CPUs is not yet implemented and they panic. 216f249345SYatharth Kochar * --------------------------------------------------------------------- 226f249345SYatharth Kochar */ 236f249345SYatharth Kocharfunc plat_secondary_cold_boot_setup 246f249345SYatharth Kochar /* TODO: Implement secondary CPU cold boot setup on CSS platforms */ 256f249345SYatharth Kocharcb_panic: 266f249345SYatharth Kochar b cb_panic 276f249345SYatharth Kocharendfunc plat_secondary_cold_boot_setup 286f249345SYatharth Kochar 296f249345SYatharth Kochar /* --------------------------------------------------------------------- 306f249345SYatharth Kochar * uintptr_t plat_get_my_entrypoint (void); 316f249345SYatharth Kochar * 326f249345SYatharth Kochar * Main job of this routine is to distinguish between a cold and a warm 336f249345SYatharth Kochar * boot. On CSS platforms, this distinction is based on the contents of 346f249345SYatharth Kochar * the Trusted Mailbox. It is initialised to zero by the SCP before the 356f249345SYatharth Kochar * AP cores are released from reset. Therefore, a zero mailbox means 366f249345SYatharth Kochar * it's a cold reset. 376f249345SYatharth Kochar * 386f249345SYatharth Kochar * This functions returns the contents of the mailbox, i.e.: 396f249345SYatharth Kochar * - 0 for a cold boot; 406f249345SYatharth Kochar * - the warm boot entrypoint for a warm boot. 416f249345SYatharth Kochar * --------------------------------------------------------------------- 426f249345SYatharth Kochar */ 436f249345SYatharth Kocharfunc plat_get_my_entrypoint 446f249345SYatharth Kochar ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE 456f249345SYatharth Kochar ldr r0, [r0] 466f249345SYatharth Kochar bx lr 476f249345SYatharth Kocharendfunc plat_get_my_entrypoint 486f249345SYatharth Kochar 496f249345SYatharth Kochar /* ----------------------------------------------------------- 506f249345SYatharth Kochar * unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr) 516f249345SYatharth Kochar * Utility function to calculate the core position by 526f249345SYatharth Kochar * swapping the cluster order. This is necessary in order to 536f249345SYatharth Kochar * match the format of the boot information passed by the SCP 546f249345SYatharth Kochar * and read in plat_is_my_cpu_primary below. 556f249345SYatharth Kochar * ----------------------------------------------------------- 566f249345SYatharth Kochar */ 576f249345SYatharth Kocharfunc css_calc_core_pos_swap_cluster 586f249345SYatharth Kochar and r1, r0, #MPIDR_CPU_MASK 596f249345SYatharth Kochar and r0, r0, #MPIDR_CLUSTER_MASK 606f249345SYatharth Kochar eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order 616f249345SYatharth Kochar add r0, r1, r0, LSR #6 626f249345SYatharth Kochar bx lr 636f249345SYatharth Kocharendfunc css_calc_core_pos_swap_cluster 646f249345SYatharth Kochar 656f249345SYatharth Kochar /* ----------------------------------------------------- 666f249345SYatharth Kochar * unsigned int plat_is_my_cpu_primary (void); 676f249345SYatharth Kochar * 686f249345SYatharth Kochar * Find out whether the current cpu is the primary 696f249345SYatharth Kochar * cpu (applicable ony after a cold boot) 706f249345SYatharth Kochar * ----------------------------------------------------- 716f249345SYatharth Kochar */ 7218e279ebSSoby Mathew#if CSS_USE_SCMI_SDS_DRIVER 7318e279ebSSoby Mathewfunc plat_is_my_cpu_primary 7418e279ebSSoby Mathew mov r10, lr 7518e279ebSSoby Mathew bl plat_my_core_pos 7618e279ebSSoby Mathew mov r4, r0 7718e279ebSSoby Mathew bl sds_get_primary_cpu_id 7818e279ebSSoby Mathew /* Check for error */ 7918e279ebSSoby Mathew mov r1, #0xffffffff 8018e279ebSSoby Mathew cmp r0, r1 8118e279ebSSoby Mathew beq 1f 8218e279ebSSoby Mathew cmp r0, r4 8318e279ebSSoby Mathew moveq r0, #1 8418e279ebSSoby Mathew movne r0, #0 8518e279ebSSoby Mathew bx r10 8618e279ebSSoby Mathew1: 8718e279ebSSoby Mathew no_ret plat_panic_handler 8818e279ebSSoby Mathewendfunc plat_is_my_cpu_primary 8918e279ebSSoby Mathew#else 906f249345SYatharth Kocharfunc plat_is_my_cpu_primary 916f249345SYatharth Kochar mov r10, lr 926f249345SYatharth Kochar bl plat_my_core_pos 936f249345SYatharth Kochar ldr r1, =SCP_BOOT_CFG_ADDR 946f249345SYatharth Kochar ldr r1, [r1] 956f249345SYatharth Kochar ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ 966f249345SYatharth Kochar #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 976f249345SYatharth Kochar cmp r0, r1 986f249345SYatharth Kochar moveq r0, #1 996f249345SYatharth Kochar movne r0, #0 1006f249345SYatharth Kochar bx r10 1016f249345SYatharth Kocharendfunc plat_is_my_cpu_primary 10218e279ebSSoby Mathew#endif 103