103a3042bSYatharth Kochar/* 2*3fb52e41SRyan Everett * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 303a3042bSYatharth Kochar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 503a3042bSYatharth Kochar */ 603a3042bSYatharth Kochar 703a3042bSYatharth Kochar#include <arch.h> 803a3042bSYatharth Kochar#include <asm_macros.S> 903a3042bSYatharth Kochar#include <assert_macros.S> 1003a3042bSYatharth Kochar#include <cortex_a32.h> 1103a3042bSYatharth Kochar#include <cpu_macros.S> 1203a3042bSYatharth Kochar 1303a3042bSYatharth Kochar 1403a3042bSYatharth Kochar /* --------------------------------------------- 1503a3042bSYatharth Kochar * Disable intra-cluster coherency 1603a3042bSYatharth Kochar * Clobbers: r0-r1 1703a3042bSYatharth Kochar * --------------------------------------------- 1803a3042bSYatharth Kochar */ 1903a3042bSYatharth Kocharfunc cortex_a32_disable_smp 2003a3042bSYatharth Kochar ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1 2103a3042bSYatharth Kochar bic r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT 2203a3042bSYatharth Kochar stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1 2303a3042bSYatharth Kochar isb 2403a3042bSYatharth Kochar dsb sy 2503a3042bSYatharth Kochar bx lr 2603a3042bSYatharth Kocharendfunc cortex_a32_disable_smp 2703a3042bSYatharth Kochar 2803a3042bSYatharth Kochar /* ------------------------------------------------- 2903a3042bSYatharth Kochar * The CPU Ops reset function for Cortex-A32. 3003a3042bSYatharth Kochar * Clobbers: r0-r1 3103a3042bSYatharth Kochar * ------------------------------------------------- 3203a3042bSYatharth Kochar */ 3303a3042bSYatharth Kocharfunc cortex_a32_reset_func 3403a3042bSYatharth Kochar /* --------------------------------------------- 3503a3042bSYatharth Kochar * Enable the SMP bit. 3603a3042bSYatharth Kochar * --------------------------------------------- 3703a3042bSYatharth Kochar */ 3803a3042bSYatharth Kochar ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1 3903a3042bSYatharth Kochar orr r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT 4003a3042bSYatharth Kochar stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1 4103a3042bSYatharth Kochar isb 4203a3042bSYatharth Kochar bx lr 4303a3042bSYatharth Kocharendfunc cortex_a32_reset_func 4403a3042bSYatharth Kochar 4503a3042bSYatharth Kochar /* ---------------------------------------------------- 4603a3042bSYatharth Kochar * The CPU Ops core power down function for Cortex-A32. 4703a3042bSYatharth Kochar * Clobbers: r0-r3 4803a3042bSYatharth Kochar * ---------------------------------------------------- 4903a3042bSYatharth Kochar */ 5003a3042bSYatharth Kocharfunc cortex_a32_core_pwr_dwn 519f3ee61cSSoby Mathew /* r12 is pushed to meet the 8 byte stack alignment requirement */ 529f3ee61cSSoby Mathew push {r12, lr} 5303a3042bSYatharth Kochar 5403a3042bSYatharth Kochar /* Assert if cache is enabled */ 55044bb2faSAntonio Nino Diaz#if ENABLE_ASSERTIONS 5603a3042bSYatharth Kochar ldcopr r0, SCTLR 5703a3042bSYatharth Kochar tst r0, #SCTLR_C_BIT 5803a3042bSYatharth Kochar ASM_ASSERT(eq) 5903a3042bSYatharth Kochar#endif 6003a3042bSYatharth Kochar 6103a3042bSYatharth Kochar /* --------------------------------------------- 6203a3042bSYatharth Kochar * Flush L1 caches. 6303a3042bSYatharth Kochar * --------------------------------------------- 6403a3042bSYatharth Kochar */ 6503a3042bSYatharth Kochar mov r0, #DC_OP_CISW 6603a3042bSYatharth Kochar bl dcsw_op_level1 6703a3042bSYatharth Kochar 6803a3042bSYatharth Kochar /* --------------------------------------------- 6903a3042bSYatharth Kochar * Come out of intra cluster coherency 7003a3042bSYatharth Kochar * --------------------------------------------- 7103a3042bSYatharth Kochar */ 729f3ee61cSSoby Mathew pop {r12, lr} 7303a3042bSYatharth Kochar b cortex_a32_disable_smp 7403a3042bSYatharth Kocharendfunc cortex_a32_core_pwr_dwn 7503a3042bSYatharth Kochar 7603a3042bSYatharth Kochar /* ------------------------------------------------------- 7703a3042bSYatharth Kochar * The CPU Ops cluster power down function for Cortex-A32. 7803a3042bSYatharth Kochar * Clobbers: r0-r3 7903a3042bSYatharth Kochar * ------------------------------------------------------- 8003a3042bSYatharth Kochar */ 8103a3042bSYatharth Kocharfunc cortex_a32_cluster_pwr_dwn 829f3ee61cSSoby Mathew /* r12 is pushed to meet the 8 byte stack alignment requirement */ 839f3ee61cSSoby Mathew push {r12, lr} 8403a3042bSYatharth Kochar 8503a3042bSYatharth Kochar /* Assert if cache is enabled */ 86044bb2faSAntonio Nino Diaz#if ENABLE_ASSERTIONS 8703a3042bSYatharth Kochar ldcopr r0, SCTLR 8803a3042bSYatharth Kochar tst r0, #SCTLR_C_BIT 8903a3042bSYatharth Kochar ASM_ASSERT(eq) 9003a3042bSYatharth Kochar#endif 9103a3042bSYatharth Kochar 9203a3042bSYatharth Kochar /* --------------------------------------------- 9303a3042bSYatharth Kochar * Flush L1 cache. 9403a3042bSYatharth Kochar * --------------------------------------------- 9503a3042bSYatharth Kochar */ 9603a3042bSYatharth Kochar mov r0, #DC_OP_CISW 9703a3042bSYatharth Kochar bl dcsw_op_level1 9803a3042bSYatharth Kochar 9903a3042bSYatharth Kochar /* --------------------------------------------- 10003a3042bSYatharth Kochar * Disable the optional ACP. 10103a3042bSYatharth Kochar * --------------------------------------------- 10203a3042bSYatharth Kochar */ 10303a3042bSYatharth Kochar bl plat_disable_acp 10403a3042bSYatharth Kochar 10503a3042bSYatharth Kochar /* --------------------------------------------- 10603a3042bSYatharth Kochar * Flush L2 cache. 10703a3042bSYatharth Kochar * --------------------------------------------- 10803a3042bSYatharth Kochar */ 10903a3042bSYatharth Kochar mov r0, #DC_OP_CISW 11003a3042bSYatharth Kochar bl dcsw_op_level2 11103a3042bSYatharth Kochar 11203a3042bSYatharth Kochar /* --------------------------------------------- 11303a3042bSYatharth Kochar * Come out of intra cluster coherency 11403a3042bSYatharth Kochar * --------------------------------------------- 11503a3042bSYatharth Kochar */ 1169f3ee61cSSoby Mathew pop {r12, lr} 11703a3042bSYatharth Kochar b cortex_a32_disable_smp 11803a3042bSYatharth Kocharendfunc cortex_a32_cluster_pwr_dwn 11903a3042bSYatharth Kochar 1205dd9dbb5SJeenu Viswambharandeclare_cpu_ops cortex_a32, CORTEX_A32_MIDR, \ 1215dd9dbb5SJeenu Viswambharan cortex_a32_reset_func, \ 1225dd9dbb5SJeenu Viswambharan cortex_a32_core_pwr_dwn, \ 1235dd9dbb5SJeenu Viswambharan cortex_a32_cluster_pwr_dwn 124