16ff43c26SEtienne Carriere/* 2*3fb52e41SRyan Everett * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. 36ff43c26SEtienne Carriere * 46ff43c26SEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 56ff43c26SEtienne Carriere */ 66ff43c26SEtienne Carriere 76ff43c26SEtienne Carriere#include <arch.h> 86ff43c26SEtienne Carriere#include <asm_macros.S> 96ff43c26SEtienne Carriere#include <assert_macros.S> 106ff43c26SEtienne Carriere#include <cortex_a7.h> 116ff43c26SEtienne Carriere#include <cpu_macros.S> 126ff43c26SEtienne Carriere 136ff43c26SEtienne Carriere .macro assert_cache_enabled 146ff43c26SEtienne Carriere#if ENABLE_ASSERTIONS 156ff43c26SEtienne Carriere ldcopr r0, SCTLR 166ff43c26SEtienne Carriere tst r0, #SCTLR_C_BIT 176ff43c26SEtienne Carriere ASM_ASSERT(eq) 186ff43c26SEtienne Carriere#endif 196ff43c26SEtienne Carriere .endm 206ff43c26SEtienne Carriere 216ff43c26SEtienne Carrierefunc cortex_a7_disable_smp 226ff43c26SEtienne Carriere ldcopr r0, ACTLR 236ff43c26SEtienne Carriere bic r0, #CORTEX_A7_ACTLR_SMP_BIT 246ff43c26SEtienne Carriere stcopr r0, ACTLR 256ff43c26SEtienne Carriere isb 266ff43c26SEtienne Carriere dsb sy 276ff43c26SEtienne Carriere bx lr 286ff43c26SEtienne Carriereendfunc cortex_a7_disable_smp 296ff43c26SEtienne Carriere 306ff43c26SEtienne Carrierefunc cortex_a7_enable_smp 316ff43c26SEtienne Carriere ldcopr r0, ACTLR 326ff43c26SEtienne Carriere orr r0, #CORTEX_A7_ACTLR_SMP_BIT 336ff43c26SEtienne Carriere stcopr r0, ACTLR 346ff43c26SEtienne Carriere isb 356ff43c26SEtienne Carriere bx lr 366ff43c26SEtienne Carriereendfunc cortex_a7_enable_smp 376ff43c26SEtienne Carriere 386ff43c26SEtienne Carrierefunc cortex_a7_reset_func 396ff43c26SEtienne Carriere b cortex_a7_enable_smp 406ff43c26SEtienne Carriereendfunc cortex_a7_reset_func 416ff43c26SEtienne Carriere 426ff43c26SEtienne Carrierefunc cortex_a7_core_pwr_dwn 436ff43c26SEtienne Carriere push {r12, lr} 446ff43c26SEtienne Carriere 456ff43c26SEtienne Carriere assert_cache_enabled 466ff43c26SEtienne Carriere 476ff43c26SEtienne Carriere /* Flush L1 cache */ 486ff43c26SEtienne Carriere mov r0, #DC_OP_CISW 496ff43c26SEtienne Carriere bl dcsw_op_level1 506ff43c26SEtienne Carriere 516ff43c26SEtienne Carriere /* Exit cluster coherency */ 526ff43c26SEtienne Carriere pop {r12, lr} 536ff43c26SEtienne Carriere b cortex_a7_disable_smp 546ff43c26SEtienne Carriereendfunc cortex_a7_core_pwr_dwn 556ff43c26SEtienne Carriere 566ff43c26SEtienne Carrierefunc cortex_a7_cluster_pwr_dwn 576ff43c26SEtienne Carriere push {r12, lr} 586ff43c26SEtienne Carriere 596ff43c26SEtienne Carriere assert_cache_enabled 606ff43c26SEtienne Carriere 616ff43c26SEtienne Carriere /* Flush L1 caches */ 626ff43c26SEtienne Carriere mov r0, #DC_OP_CISW 636ff43c26SEtienne Carriere bl dcsw_op_level1 646ff43c26SEtienne Carriere 656ff43c26SEtienne Carriere bl plat_disable_acp 666ff43c26SEtienne Carriere 67c5c160cdSStephan Gerhold /* Flush L2 caches */ 68c5c160cdSStephan Gerhold mov r0, #DC_OP_CISW 69c5c160cdSStephan Gerhold bl dcsw_op_level2 70c5c160cdSStephan Gerhold 716ff43c26SEtienne Carriere /* Exit cluster coherency */ 726ff43c26SEtienne Carriere pop {r12, lr} 736ff43c26SEtienne Carriere b cortex_a7_disable_smp 746ff43c26SEtienne Carriereendfunc cortex_a7_cluster_pwr_dwn 756ff43c26SEtienne Carriere 766ff43c26SEtienne Carrieredeclare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \ 776ff43c26SEtienne Carriere cortex_a7_reset_func, \ 786ff43c26SEtienne Carriere cortex_a7_core_pwr_dwn, \ 796ff43c26SEtienne Carriere cortex_a7_cluster_pwr_dwn 80