Merge changes from topic "clean-up-errata-compatibility" into integration

* changes:
refactor(cpus): remove cpu specific errata funcs
refactor(cpus): directly invoke errata reporter

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.

Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "fix(cpus): flush L2 cache for Cortex-A7/12/15/17" into integration

fix(cpus): flush L2 cache for Cortex-A7/12/15/17

Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster

fix(cpus): flush L2 cache for Cortex-A7/12/15/17

Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.

Fix this by adding the L2 cache flush similar to cortex_a53.S.

Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>

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Merge changes from topic "sm/errata_refactor" into integration

* changes:
refactor(cpus): convert Cortex-A15 to use the errata framework
refactor(cpus): convert the Cortex-X3 to use the cpu help

Merge changes from topic "sm/errata_refactor" into integration

* changes:
refactor(cpus): convert Cortex-A15 to use the errata framework
refactor(cpus): convert the Cortex-X3 to use the cpu helpers
refactor(cpus): convert Cortex-X3 to use the errata framework
refactor(cpus): reorder Cortex-X3 errata by ascending order
refactor(cpus): convert the Cortex-A73 to use the cpu helpers
refactor(cpus): convert Cortex-A73 to use the errata framework
refactor(cpus): reorder Cortex-A73 errata by ascending order
refactor(cpus): convert the Cortex-A35 to use the cpu helpers
refactor(cpus): convert Cortex-A35 to use the errata framework

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refactor(cpus): convert Cortex-A15 to use the errata framework

Change-Id: I569b0da3ed5b81b4b6e9a7820d32684376a190a9
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

Merge "fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960" into integration

fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960

Cortex-A15 does not support FEAT_CSV2 so the existing workaround for
Spectre V2 is sufficient to mitigate against Spectre BHB attack

fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960

Cortex-A15 does not support FEAT_CSV2 so the existing workaround for
Spectre V2 is sufficient to mitigate against Spectre BHB attacks,
however the code needed to be updated to work with the new build flag.

Also, some code was refactored several years ago and not updated in
the Cortex-A15 library file so this patch fixes that as well.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I768c88a38c561c91019b038ac6c22b291955f18e

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Merge pull request #1882 from ambroise-arm/av/a15-errata

Apply workarounds for errata of Cortex-A15

Cortex-A15: Implement workaround for errata 827671

This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1]

Cortex-A15: Implement workaround for errata 827671

This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html

Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Cortex-A15: Implement workaround for errata 816470

Change-Id: I9755252725be25bfd0147839d7df56888424ff84
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Merge pull request #1228 from dp-arm/dp/cve_2017_5715

Workarounds for CVE-2017-5715 on A9/A15 and A17 + serial console reporting

Workaround for CVE-2017-5715 for Cortex A9, A15 and A17

A per-cpu vbar is installed that implements the workaround by
invalidating the branch target buffer (BTB) directly in the case of A9
and A17 a

Workaround for CVE-2017-5715 for Cortex A9, A15 and A17

A per-cpu vbar is installed that implements the workaround by
invalidating the branch target buffer (BTB) directly in the case of A9
and A17 and indirectly by invalidating the icache in the case of A15.

For Cortex A57 and A72 there is currently no workaround implemented
when EL3 is in AArch32 mode so report it as missing.

For other vulnerable CPUs (e.g. Cortex A73 and Cortex A75), there are
no changes since there is currently no upstream AArch32 EL3 support
for these CPUs.

Change-Id: Ib42c6ef0b3c9ff2878a9e53839de497ff736258f
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Merge pull request #1145 from etienne-lms/rfc-armv7-2

Support ARMv7 architectures

ARMv7: introduce Cortex-A15

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>