1727e5238SSoby Mathew/* 2232c1892SBoyan Karatotev * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3727e5238SSoby Mathew * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5727e5238SSoby Mathew */ 6727e5238SSoby Mathew 7727e5238SSoby Mathew#include <asm_macros.S> 809d40e0eSAntonio Nino Diaz#include <lib/psci/psci.h> 9727e5238SSoby Mathew#include <platform_def.h> 10727e5238SSoby Mathew 11727e5238SSoby Mathew .globl psci_do_pwrdown_cache_maintenance 12727e5238SSoby Mathew .globl psci_do_pwrup_cache_maintenance 13727e5238SSoby Mathew 14727e5238SSoby Mathew/* ----------------------------------------------------------------------- 15*aadb4b56SBoyan Karatotev * void psci_do_pwrdown_cache_maintenance(void); 16727e5238SSoby Mathew * 17*aadb4b56SBoyan Karatotev * This function turns off data caches and also ensures that stack memory 18*aadb4b56SBoyan Karatotev * is correctly flushed out to avoid coherency issues due to a change in 19*aadb4b56SBoyan Karatotev * its memory attributes. 20727e5238SSoby Mathew * ----------------------------------------------------------------------- 21727e5238SSoby Mathew */ 22727e5238SSoby Mathewfunc psci_do_pwrdown_cache_maintenance 23727e5238SSoby Mathew push {r4, lr} 24*aadb4b56SBoyan Karatotev bl plat_get_my_stack 25727e5238SSoby Mathew 26*aadb4b56SBoyan Karatotev /* Turn off the D-cache */ 27*aadb4b56SBoyan Karatotev ldcopr r1, SCTLR 28*aadb4b56SBoyan Karatotev bic r1, #SCTLR_C_BIT 29*aadb4b56SBoyan Karatotev stcopr r1, SCTLR 30*aadb4b56SBoyan Karatotev isb 31727e5238SSoby Mathew 32727e5238SSoby Mathew /* --------------------------------------------- 33*aadb4b56SBoyan Karatotev * Calculate and store the size of the used 34*aadb4b56SBoyan Karatotev * stack memory in r1. 35727e5238SSoby Mathew * --------------------------------------------- 36727e5238SSoby Mathew */ 37*aadb4b56SBoyan Karatotev mov r4, r0 38*aadb4b56SBoyan Karatotev mov r1, sp 39*aadb4b56SBoyan Karatotev sub r1, r0, r1 40*aadb4b56SBoyan Karatotev mov r0, sp 41*aadb4b56SBoyan Karatotev bl flush_dcache_range 42*aadb4b56SBoyan Karatotev 43*aadb4b56SBoyan Karatotev /* --------------------------------------------- 44*aadb4b56SBoyan Karatotev * Calculate and store the size of the unused 45*aadb4b56SBoyan Karatotev * stack memory in r1. Calculate and store the 46*aadb4b56SBoyan Karatotev * stack base address in r0. 47*aadb4b56SBoyan Karatotev * --------------------------------------------- 48*aadb4b56SBoyan Karatotev */ 49*aadb4b56SBoyan Karatotev sub r0, r4, #PLATFORM_STACK_SIZE 50*aadb4b56SBoyan Karatotev sub r1, sp, r0 51*aadb4b56SBoyan Karatotev bl inv_dcache_range 52*aadb4b56SBoyan Karatotev 53*aadb4b56SBoyan Karatotev pop {r4, pc} 54727e5238SSoby Mathewendfunc psci_do_pwrdown_cache_maintenance 55727e5238SSoby Mathew 56727e5238SSoby Mathew 57727e5238SSoby Mathew/* ----------------------------------------------------------------------- 58727e5238SSoby Mathew * void psci_do_pwrup_cache_maintenance(void); 59727e5238SSoby Mathew * 60727e5238SSoby Mathew * This function performs cache maintenance after this cpu is powered up. 61727e5238SSoby Mathew * Currently, this involves managing the used stack memory before turning 62727e5238SSoby Mathew * on the data cache. 63727e5238SSoby Mathew * ----------------------------------------------------------------------- 64727e5238SSoby Mathew */ 65727e5238SSoby Mathewfunc psci_do_pwrup_cache_maintenance 669f3ee61cSSoby Mathew /* r12 is pushed to meet the 8 byte stack alignment requirement */ 679f3ee61cSSoby Mathew push {r12, lr} 68727e5238SSoby Mathew 69727e5238SSoby Mathew /* --------------------------------------------- 70727e5238SSoby Mathew * Ensure any inflight stack writes have made it 71727e5238SSoby Mathew * to main memory. 72727e5238SSoby Mathew * --------------------------------------------- 73727e5238SSoby Mathew */ 74727e5238SSoby Mathew dmb st 75727e5238SSoby Mathew 76727e5238SSoby Mathew /* --------------------------------------------- 77727e5238SSoby Mathew * Calculate and store the size of the used 78727e5238SSoby Mathew * stack memory in r1. Calculate and store the 79727e5238SSoby Mathew * stack base address in r0. 80727e5238SSoby Mathew * --------------------------------------------- 81727e5238SSoby Mathew */ 82727e5238SSoby Mathew bl plat_get_my_stack 83727e5238SSoby Mathew mov r1, sp 84727e5238SSoby Mathew sub r1, r0, r1 85727e5238SSoby Mathew mov r0, sp 86727e5238SSoby Mathew bl inv_dcache_range 87727e5238SSoby Mathew 88727e5238SSoby Mathew /* --------------------------------------------- 89727e5238SSoby Mathew * Enable the data cache. 90727e5238SSoby Mathew * --------------------------------------------- 91727e5238SSoby Mathew */ 92727e5238SSoby Mathew ldcopr r0, SCTLR 93727e5238SSoby Mathew orr r0, r0, #SCTLR_C_BIT 94727e5238SSoby Mathew stcopr r0, SCTLR 95727e5238SSoby Mathew isb 96727e5238SSoby Mathew 979f3ee61cSSoby Mathew pop {r12, pc} 98727e5238SSoby Mathewendfunc psci_do_pwrup_cache_maintenance 99