11ca8d023SEtienne Carriere/* 2*3fb52e41SRyan Everett * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. 31ca8d023SEtienne Carriere * 41ca8d023SEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 51ca8d023SEtienne Carriere */ 61ca8d023SEtienne Carriere 71ca8d023SEtienne Carriere#include <arch.h> 81ca8d023SEtienne Carriere#include <asm_macros.S> 91ca8d023SEtienne Carriere#include <assert_macros.S> 101ca8d023SEtienne Carriere#include <cortex_a12.h> 111ca8d023SEtienne Carriere#include <cpu_macros.S> 121ca8d023SEtienne Carriere 131ca8d023SEtienne Carriere .macro assert_cache_enabled 141ca8d023SEtienne Carriere#if ENABLE_ASSERTIONS 151ca8d023SEtienne Carriere ldcopr r0, SCTLR 161ca8d023SEtienne Carriere tst r0, #SCTLR_C_BIT 171ca8d023SEtienne Carriere ASM_ASSERT(eq) 181ca8d023SEtienne Carriere#endif 191ca8d023SEtienne Carriere .endm 201ca8d023SEtienne Carriere 211ca8d023SEtienne Carrierefunc cortex_a12_disable_smp 221ca8d023SEtienne Carriere ldcopr r0, ACTLR 231ca8d023SEtienne Carriere bic r0, #CORTEX_A12_ACTLR_SMP_BIT 241ca8d023SEtienne Carriere stcopr r0, ACTLR 251ca8d023SEtienne Carriere isb 261ca8d023SEtienne Carriere dsb sy 271ca8d023SEtienne Carriere bx lr 281ca8d023SEtienne Carriereendfunc cortex_a12_disable_smp 291ca8d023SEtienne Carriere 301ca8d023SEtienne Carrierefunc cortex_a12_enable_smp 311ca8d023SEtienne Carriere ldcopr r0, ACTLR 321ca8d023SEtienne Carriere orr r0, #CORTEX_A12_ACTLR_SMP_BIT 331ca8d023SEtienne Carriere stcopr r0, ACTLR 341ca8d023SEtienne Carriere isb 351ca8d023SEtienne Carriere bx lr 361ca8d023SEtienne Carriereendfunc cortex_a12_enable_smp 371ca8d023SEtienne Carriere 381ca8d023SEtienne Carrierefunc cortex_a12_reset_func 391ca8d023SEtienne Carriere b cortex_a12_enable_smp 401ca8d023SEtienne Carriereendfunc cortex_a12_reset_func 411ca8d023SEtienne Carriere 421ca8d023SEtienne Carrierefunc cortex_a12_core_pwr_dwn 431ca8d023SEtienne Carriere push {r12, lr} 441ca8d023SEtienne Carriere 451ca8d023SEtienne Carriere assert_cache_enabled 461ca8d023SEtienne Carriere 471ca8d023SEtienne Carriere /* Flush L1 cache */ 481ca8d023SEtienne Carriere mov r0, #DC_OP_CISW 491ca8d023SEtienne Carriere bl dcsw_op_level1 501ca8d023SEtienne Carriere 511ca8d023SEtienne Carriere /* Exit cluster coherency */ 521ca8d023SEtienne Carriere pop {r12, lr} 531ca8d023SEtienne Carriere b cortex_a12_disable_smp 541ca8d023SEtienne Carriereendfunc cortex_a12_core_pwr_dwn 551ca8d023SEtienne Carriere 561ca8d023SEtienne Carrierefunc cortex_a12_cluster_pwr_dwn 571ca8d023SEtienne Carriere push {r12, lr} 581ca8d023SEtienne Carriere 591ca8d023SEtienne Carriere assert_cache_enabled 601ca8d023SEtienne Carriere 611ca8d023SEtienne Carriere /* Flush L1 caches */ 621ca8d023SEtienne Carriere mov r0, #DC_OP_CISW 631ca8d023SEtienne Carriere bl dcsw_op_level1 641ca8d023SEtienne Carriere 651ca8d023SEtienne Carriere bl plat_disable_acp 661ca8d023SEtienne Carriere 67c5c160cdSStephan Gerhold /* Flush L2 caches */ 68c5c160cdSStephan Gerhold mov r0, #DC_OP_CISW 69c5c160cdSStephan Gerhold bl dcsw_op_level2 70c5c160cdSStephan Gerhold 711ca8d023SEtienne Carriere /* Exit cluster coherency */ 721ca8d023SEtienne Carriere pop {r12, lr} 731ca8d023SEtienne Carriere b cortex_a12_disable_smp 741ca8d023SEtienne Carriereendfunc cortex_a12_cluster_pwr_dwn 751ca8d023SEtienne Carriere 761ca8d023SEtienne Carrieredeclare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \ 771ca8d023SEtienne Carriere cortex_a12_reset_func, \ 781ca8d023SEtienne Carriere cortex_a12_core_pwr_dwn, \ 791ca8d023SEtienne Carriere cortex_a12_cluster_pwr_dwn 80