| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | neoverse_v1.S | 34 msr NEOVERSE_V1_CPUPSELR_EL3, x0
36 msr NEOVERSE_V1_CPUPOR_EL3, x0
38 msr NEOVERSE_V1_CPUPMR_EL3, x0
40 msr NEOVERSE_V1_CPUPCR_EL3, x0
44 msr NEOVERSE_V1_CPUPSELR_EL3, x0
46 msr NEOVERSE_V1_CPUPOR_EL3, x0
48 msr NEOVERSE_V1_CPUPMR_EL3, x0
50 msr NEOVERSE_V1_CPUPCR_EL3, x0
54 msr NEOVERSE_V1_CPUPSELR_EL3, x0
56 msr NEOVERSE_V1_CPUPOR_EL3, x0
[all …]
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| H A D | cortex_a77.S | 38 msr CORTEX_A77_CPUPSELR_EL3, x0
40 msr CORTEX_A77_CPUPOR_EL3, x0
42 msr CORTEX_A77_CPUPMR_EL3, x0
44 msr CORTEX_A77_CPUPCR_EL3, x0
46 msr CORTEX_A77_CPUPSELR_EL3, x0
48 msr CORTEX_A77_CPUPOR_EL3, x0
50 msr CORTEX_A77_CPUPMR_EL3, x0
54 msr CORTEX_A77_CPUPSELR_EL3, x0
56 msr CORTEX_A77_CPUPOR_EL3, x0
58 msr CORTEX_A77_CPUPMR_EL3, x0
[all …]
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| H A D | cortex_a78.S | 48 msr S3_6_c15_c8_0, xzr
50 msr S3_6_c15_c8_2, x0
52 msr S3_6_c15_c8_3, x0
54 msr S3_6_c15_c8_1, x0
57 msr S3_6_c15_c8_0, x0
59 msr S3_6_c15_c8_2, x0
61 msr S3_6_c15_c8_3, x0
63 msr S3_6_c15_c8_1, x0
66 msr S3_6_c15_c8_0, x0
68 msr S3_6_c15_c8_2, x0
[all …]
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| H A D | cortex_a710.S | 54 msr S3_6_C15_C8_0, x0
56 msr S3_6_C15_C8_2, x0
58 msr S3_6_C15_C8_3, x0
60 msr S3_6_C15_C8_1, x0
63 msr S3_6_C15_C8_0, x0
65 msr S3_6_C15_C8_2, x0
67 msr S3_6_C15_C8_3, x0
69 msr S3_6_C15_C8_1, x0
72 msr S3_6_C15_C8_0, x0
74 msr S3_6_C15_C8_2, x0
[all …]
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| H A D | cortex_x2.S | 54 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
56 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
58 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
60 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
63 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
65 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
67 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
69 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
72 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
74 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
[all …]
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| H A D | cortex_a78_ae.S | 34 msr S3_6_c15_c8_0, xzr
36 msr S3_6_c15_c8_2, x0
38 msr S3_6_c15_c8_3, x0
40 msr S3_6_c15_c8_1, x0
43 msr S3_6_c15_c8_0, x0
45 msr S3_6_c15_c8_2, x0
47 msr S3_6_c15_c8_3, x0
49 msr S3_6_c15_c8_1, x0
52 msr S3_6_c15_c8_0, x0
54 msr S3_6_c15_c8_2, x0
[all …]
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| H A D | cortex_a76ae.S | 46 msr CORTEX_A76AE_CPUPSELR_EL3,x0
48 msr CORTEX_A76AE_CPUPOR_EL3,x0
50 msr CORTEX_A76AE_CPUPMR_EL3,x0
52 msr CORTEX_A76AE_CPUPCR_EL3,x0
55 msr CORTEX_A76AE_CPUPSELR_EL3,x0
57 msr CORTEX_A76AE_CPUPOR_EL3,x0
59 msr CORTEX_A76AE_CPUPMR_EL3,x0
61 msr CORTEX_A76AE_CPUPCR_EL3,x0
64 msr CORTEX_A76AE_CPUPSELR_EL3,x0
66 msr CORTEX_A76AE_CPUPOR_EL3,x0
[all …]
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| H A D | neoverse_n1.S | 47 msr CPUPSELR_EL3, x0
49 msr CPUPOR_EL3, x0
51 msr CPUPMR_EL3, x0
53 msr CPUPCR_EL3, x0
122 msr CPUPSELR_EL3, x0
124 msr CPUPOR_EL3, x0
126 msr CPUPMR_EL3, x0
128 msr CPUPCR_EL3, x0
142 msr S3_6_C15_C8_0, x0
144 msr S3_6_C15_C8_2, x0
[all …]
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| H A D | neoverse_n2.S | 35 msr S3_6_c15_c8_0,x0
37 msr S3_6_c15_c8_2,x0
39 msr S3_6_c15_c8_3,x0
41 msr S3_6_c15_c8_1,x0
43 msr S3_6_c15_c8_0,x0
45 msr S3_6_c15_c8_2,x0
47 msr S3_6_c15_c8_3,x0
49 msr S3_6_c15_c8_1,x0
59 msr ERRSELR_EL1, xzr
62 msr ERXCTLR_EL1, x1
[all …]
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| H A D | cortex_a715.S | 50 msr CORTEX_A715_CPUPSELR_EL3, x0
53 msr CORTEX_A715_CPUPOR_EL3, x0
55 msr CORTEX_A715_CPUPMR_EL3, x0
62 msr CORTEX_A715_CPUPCR_EL3, x1
115 msr CORTEX_A715_CPUPSELR_EL3, x0
118 msr CORTEX_A715_CPUPOR_EL3, x0
120 msr CORTEX_A715_CPUPMR_EL3, x0
129 msr CORTEX_A715_CPUPCR_EL3, x0
165 msr CORTEX_A715_CPUPSELR_EL3, x0
167 msr CORTEX_A715_CPUPOR_EL3, x0
[all …]
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| H A D | c1_premium.S | 89 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0
91 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0
93 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0
95 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0
99 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0
101 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0
103 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0
105 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0
119 msr SSBS, xzr
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| H A D | cortex_a510.S | 32 msr ERRSELR_EL1, xzr
37 msr ERRSELR_EL1, x0
42 msr ERRSELR_EL1, x0
46 msr ERRSELR_EL1, x2
54 msr S3_6_C15_C4_0, x0
58 msr S3_6_C15_C4_2, x0
62 msr S3_6_C15_C4_3, x0
66 msr S3_6_C15_C4_1, x0
82 msr S3_6_C15_C4_0, x0
87 msr S3_6_C15_C4_2, x0
[all …]
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| H A D | c1_ultra.S | 93 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0
95 msr C1_ULTRA_IMP_CPUPOR_EL3, x0
97 msr C1_ULTRA_IMP_CPUPMR_EL3, x0
99 msr C1_ULTRA_IMP_CPUPCR_EL3, x0
102 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0
104 msr C1_ULTRA_IMP_CPUPOR_EL3, x0
106 msr C1_ULTRA_IMP_CPUPMR_EL3, x0
108 msr C1_ULTRA_IMP_CPUPCR_EL3, x0
125 msr SSBS, xzr
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| H A D | cortex_a78c.S | 42 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
44 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
46 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
48 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
67 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
69 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
71 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
73 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
|
| H A D | cortex_x4.S | 82 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
84 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
86 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
88 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
104 msr s3_6_c15_c8_0,x0 /* msr cpupselr_el3, x0 */
106 msr s3_6_c15_c8_2,x0 /* msr cpupor_el3, x0 */
108 msr s3_6_c15_c8_3,x0 /* msr cpupmr_el3, x0 */
110 msr s3_6_c15_c8_1,x0 /* msr cpupcr_el3, x0 */
146 msr SSBS, xzr
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| H A D | neoverse_v3.S | 32 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
34 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
36 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
38 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
85 msr SSBS, xzr
|
| H A D | cortex_x925.S | 44 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
46 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
48 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
50 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
77 msr SSBS, xzr
|
| H A D | cortex_a55.S | 89 msr CPUPOR_EL3, x0
93 msr CPUPMR_EL3, x0
96 msr CPUPCR_EL3, x0
98 msr CPUPSELR_EL3, x0
101 msr CPUPOR_EL3, x0
105 msr CPUPMR_EL3, x0
108 msr CPUPCR_EL3, x0
|
| H A D | cortex_a76.S | 62 msr CORTEX_A76_CPUACTLR2_EL1, x2
293 msr CORTEX_A76_CPUACTLR2_EL1, x3
335 msr CORTEX_A76_CPUACTLR2_EL1, x1
413 msr S3_6_C15_C8_0, x0
415 msr S3_6_C15_C8_2, x0
417 msr S3_6_C15_C8_3, x0
419 msr S3_6_C15_C8_1, x0
422 msr S3_6_C15_C8_0, x0
424 msr S3_6_C15_C8_2, x0
426 msr S3_6_C15_C8_3, x0
[all …]
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| H A D | cortex_a725.S | 66 msr CORTEX_A725_CPUPSELR_EL3, x0
70 msr CORTEX_A725_CPUPOR_EL3, x0
72 msr CORTEX_A725_CPUPMR_EL3, x0
79 msr CORTEX_A725_CPUPCR_EL3, x1
87 msr SSBS, xzr
|
| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | smccc_macros.S | 179 msr spsr_fsxc, r2
183 msr spsr_fsxc, r2
187 msr spsr_fsxc, r2
191 msr spsr_fsxc, r2
195 msr spsr_fsxc, r2
199 msr spsr_fsxc, r2
205 msr sp_usr, r4
206 msr lr_usr, r5
207 msr spsr_irq, r6
208 msr sp_irq, r7
[all …]
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | el3_common_macros.S | 46 msr sctlr_el3, x0
55 msr SCTLR2_EL3, x1
93 msr scr_el3, x0
100 msr mdcr_el3, x0
108 msr cptr_el3, x0
192 msr sctlr_el3, x0
236 msr vbar_el3, x0
411 msr spsel, #0
460 msr sctlr_el1, x28
462 msr tcr_el1, x29
[all …]
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/aarch64/ |
| H A D | nvg_helpers.S | 16 msr s3_0_c15_c1_2, x0
17 msr s3_0_c15_c1_3, x1
23 msr s3_0_c15_c1_2, x0
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| /rk3399_ARM-atf/plat/nvidia/tegra/common/aarch64/ |
| H A D | tegra_helpers.S | 79 msr CORTEX_A57_L2ECTLR_EL1, x0
86 msr CORTEX_A57_ECTLR_EL1, x0
96 msr actlr_el3, x0
100 msr actlr_el2, x0
113 msr pmintenclr_el1, x0
114 msr pmuserenr_el0, x1 // enable user mode access
124 msr cntkctl_el1, x0
338 msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
347 msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
368 msr oslar_el1, x0 /* os lock stays 0 across warm reset */
[all …]
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| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context.S | 51 msr fpsr, \hold
54 msr fpcr, \hold
58 msr fpexc32_el2, \hold
295 msr DIT, x8
332 msr S3_6_C10_C5_0, x17 /* mpam3_el3 */
418 msr APIAKeyLo_EL1, x10
419 msr APIAKeyHi_EL1, x11
476 msr APIAKeyLo_EL1, x0
477 msr APIAKeyHi_EL1, x1
478 msr APIBKeyLo_EL1, x2
[all …]
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