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/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dneoverse_v1.S34 msr NEOVERSE_V1_CPUPSELR_EL3, x0
36 msr NEOVERSE_V1_CPUPOR_EL3, x0
38 msr NEOVERSE_V1_CPUPMR_EL3, x0
40 msr NEOVERSE_V1_CPUPCR_EL3, x0
44 msr NEOVERSE_V1_CPUPSELR_EL3, x0
46 msr NEOVERSE_V1_CPUPOR_EL3, x0
48 msr NEOVERSE_V1_CPUPMR_EL3, x0
50 msr NEOVERSE_V1_CPUPCR_EL3, x0
54 msr NEOVERSE_V1_CPUPSELR_EL3, x0
56 msr NEOVERSE_V1_CPUPOR_EL3, x0
[all …]
H A Dcortex_a77.S38 msr CORTEX_A77_CPUPSELR_EL3, x0
40 msr CORTEX_A77_CPUPOR_EL3, x0
42 msr CORTEX_A77_CPUPMR_EL3, x0
44 msr CORTEX_A77_CPUPCR_EL3, x0
46 msr CORTEX_A77_CPUPSELR_EL3, x0
48 msr CORTEX_A77_CPUPOR_EL3, x0
50 msr CORTEX_A77_CPUPMR_EL3, x0
54 msr CORTEX_A77_CPUPSELR_EL3, x0
56 msr CORTEX_A77_CPUPOR_EL3, x0
58 msr CORTEX_A77_CPUPMR_EL3, x0
[all …]
H A Dcortex_a78.S48 msr S3_6_c15_c8_0, xzr
50 msr S3_6_c15_c8_2, x0
52 msr S3_6_c15_c8_3, x0
54 msr S3_6_c15_c8_1, x0
57 msr S3_6_c15_c8_0, x0
59 msr S3_6_c15_c8_2, x0
61 msr S3_6_c15_c8_3, x0
63 msr S3_6_c15_c8_1, x0
66 msr S3_6_c15_c8_0, x0
68 msr S3_6_c15_c8_2, x0
[all …]
H A Dcortex_a710.S57 msr S3_6_C15_C8_0, x0
59 msr S3_6_C15_C8_2, x0
61 msr S3_6_C15_C8_3, x0
63 msr S3_6_C15_C8_1, x0
66 msr S3_6_C15_C8_0, x0
68 msr S3_6_C15_C8_2, x0
70 msr S3_6_C15_C8_3, x0
72 msr S3_6_C15_C8_1, x0
75 msr S3_6_C15_C8_0, x0
77 msr S3_6_C15_C8_2, x0
[all …]
H A Dcortex_a78_ae.S34 msr S3_6_c15_c8_0, xzr
36 msr S3_6_c15_c8_2, x0
38 msr S3_6_c15_c8_3, x0
40 msr S3_6_c15_c8_1, x0
43 msr S3_6_c15_c8_0, x0
45 msr S3_6_c15_c8_2, x0
47 msr S3_6_c15_c8_3, x0
49 msr S3_6_c15_c8_1, x0
52 msr S3_6_c15_c8_0, x0
54 msr S3_6_c15_c8_2, x0
[all …]
H A Dcortex_x2.S57 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
59 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
61 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
63 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
66 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
68 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
70 msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
72 msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
75 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
77 msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
[all …]
H A Dcortex_a76ae.S46 msr CORTEX_A76AE_CPUPSELR_EL3,x0
48 msr CORTEX_A76AE_CPUPOR_EL3,x0
50 msr CORTEX_A76AE_CPUPMR_EL3,x0
52 msr CORTEX_A76AE_CPUPCR_EL3,x0
55 msr CORTEX_A76AE_CPUPSELR_EL3,x0
57 msr CORTEX_A76AE_CPUPOR_EL3,x0
59 msr CORTEX_A76AE_CPUPMR_EL3,x0
61 msr CORTEX_A76AE_CPUPCR_EL3,x0
64 msr CORTEX_A76AE_CPUPSELR_EL3,x0
66 msr CORTEX_A76AE_CPUPOR_EL3,x0
[all …]
H A Dneoverse_n1.S47 msr CPUPSELR_EL3, x0
49 msr CPUPOR_EL3, x0
51 msr CPUPMR_EL3, x0
53 msr CPUPCR_EL3, x0
122 msr CPUPSELR_EL3, x0
124 msr CPUPOR_EL3, x0
126 msr CPUPMR_EL3, x0
128 msr CPUPCR_EL3, x0
142 msr S3_6_C15_C8_0, x0
144 msr S3_6_C15_C8_2, x0
[all …]
H A Dwa_cve_2025_0647_cpprctx.S41 msr WA_CPUPSELR_EL3, x1
42 msr WA_CPUPOR_EL3, x2
43 msr WA_CPUPMR_EL3, x3
45 msr WA_CPUPCR_EL3, x1
93 msr WA_CPUACTLR2_EL1, x5
100 msr WA_CPUACTLR_EL1, x5
105 msr WA_CPUECTLR_EL1, x5
177 msr SCR_EL3, x5
186 msr SCR_EL3, x5
193 msr SCR_EL3, x5
[all …]
H A Dneoverse_n2.S36 msr S3_6_c15_c8_0,x0
38 msr S3_6_c15_c8_2,x0
40 msr S3_6_c15_c8_3,x0
42 msr S3_6_c15_c8_1,x0
44 msr S3_6_c15_c8_0,x0
46 msr S3_6_c15_c8_2,x0
48 msr S3_6_c15_c8_3,x0
50 msr S3_6_c15_c8_1,x0
60 msr ERRSELR_EL1, xzr
63 msr ERXCTLR_EL1, x1
[all …]
H A Dcortex_a715.S50 msr CORTEX_A715_CPUPSELR_EL3, x0
53 msr CORTEX_A715_CPUPOR_EL3, x0
55 msr CORTEX_A715_CPUPMR_EL3, x0
62 msr CORTEX_A715_CPUPCR_EL3, x1
115 msr CORTEX_A715_CPUPSELR_EL3, x0
118 msr CORTEX_A715_CPUPOR_EL3, x0
120 msr CORTEX_A715_CPUPMR_EL3, x0
129 msr CORTEX_A715_CPUPCR_EL3, x0
165 msr CORTEX_A715_CPUPSELR_EL3, x0
167 msr CORTEX_A715_CPUPOR_EL3, x0
[all …]
H A Dc1_nano.S57 msr C1_NANO_IMP_CPUPSELR_EL3, x0
60 msr C1_NANO_IMP_CPUPOR_EL3, x0
62 msr C1_NANO_IMP_CPUPMR_EL3, x0
65 msr C1_NANO_IMP_CPUPCR_EL3, x0
68 msr C1_NANO_IMP_CPUPSELR_EL3, x0
71 msr C1_NANO_IMP_CPUPOR_EL3, x0
73 msr C1_NANO_IMP_CPUPMR_EL3, x0
76 msr C1_NANO_IMP_CPUPCR_EL3, x0
124 msr SSBS, xzr
H A Dcortex_a510.S32 msr ERRSELR_EL1, xzr
37 msr ERRSELR_EL1, x0
42 msr ERRSELR_EL1, x0
46 msr ERRSELR_EL1, x2
54 msr S3_6_C15_C4_0, x0
58 msr S3_6_C15_C4_2, x0
62 msr S3_6_C15_C4_3, x0
66 msr S3_6_C15_C4_1, x0
82 msr S3_6_C15_C4_0, x0
87 msr S3_6_C15_C4_2, x0
[all …]
H A Dneoverse_v3.S35 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
37 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
39 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
41 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
65 msr NEOVERSE_V3_CPUPSELR_EL3, x0
67 msr NEOVERSE_V3_CPUPOR_EL3, x0
69 msr NEOVERSE_V3_CPUPMR_EL3, x0
71 msr NEOVERSE_V3_CPUPCR_EL3, x0
83 msr NEOVERSE_V3_CPUPWRCTLR_EL1, x0
161 msr SSBS, xzr
H A Dc1_premium.S72 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0
74 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0
76 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0
78 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0
82 msr C1_PREMIUM_IMP_CPUPSELR_EL3, x0
84 msr C1_PREMIUM_IMP_CPUPOR_EL3, x0
86 msr C1_PREMIUM_IMP_CPUPMR_EL3, x0
88 msr C1_PREMIUM_IMP_CPUPCR_EL3, x0
137 msr SSBS, xzr
H A Dc1_ultra.S76 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0
78 msr C1_ULTRA_IMP_CPUPOR_EL3, x0
80 msr C1_ULTRA_IMP_CPUPMR_EL3, x0
82 msr C1_ULTRA_IMP_CPUPCR_EL3, x0
85 msr C1_ULTRA_IMP_CPUPSELR_EL3, x0
87 msr C1_ULTRA_IMP_CPUPOR_EL3, x0
89 msr C1_ULTRA_IMP_CPUPMR_EL3, x0
91 msr C1_ULTRA_IMP_CPUPCR_EL3, x0
143 msr SSBS, xzr
H A Dcortex_a78c.S42 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
44 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
46 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
48 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
67 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
69 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
71 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
73 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
H A Dcortex_x4.S85 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
87 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
89 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
91 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
107 msr s3_6_c15_c8_0,x0 /* msr cpupselr_el3, x0 */
109 msr s3_6_c15_c8_2,x0 /* msr cpupor_el3, x0 */
111 msr s3_6_c15_c8_3,x0 /* msr cpupmr_el3, x0 */
113 msr s3_6_c15_c8_1,x0 /* msr cpupcr_el3, x0 */
172 msr SSBS, xzr
/rk3399_ARM-atf/include/arch/aarch32/
H A Dsmccc_macros.S179 msr spsr_fsxc, r2
183 msr spsr_fsxc, r2
187 msr spsr_fsxc, r2
191 msr spsr_fsxc, r2
195 msr spsr_fsxc, r2
199 msr spsr_fsxc, r2
205 msr sp_usr, r4
206 msr lr_usr, r5
207 msr spsr_irq, r6
208 msr sp_irq, r7
[all …]
/rk3399_ARM-atf/include/arch/aarch64/
H A Del3_common_macros.S46 msr sctlr_el3, x0
55 msr SCTLR2_EL3, x1
88 msr scr_el3, x0
95 msr mdcr_el3, x0
103 msr cptr_el3, x0
114 msr cscr_el3, x0
119 msr cctlr_el3, xzr
204 msr sctlr_el3, x0
251 msr cptr_el3, x0
429 msr spsel, #0
[all …]
/rk3399_ARM-atf/lib/el3_runtime/aarch64/
H A Dcontext.S51 msr fpsr, \hold
54 msr fpcr, \hold
58 msr fpexc32_el2, \hold
295 msr DIT, x8
332 msr S3_6_C10_C5_0, x17 /* mpam3_el3 */
384 msr AMCNTENCLR0_EL0, x9
435 msr APIAKeyLo_EL1, x10
436 msr APIAKeyHi_EL1, x11
451 msr ddc_el0, c26
500 msr spsel, #MODE_SP_EL0
[all …]
/rk3399_ARM-atf/bl31/aarch64/
H A Dcrash_reporting.S186 msr tpidr_el3, x0
192 msr pmcr_el0, x0
194 msr far_el1, x1
195 msr elr_el1, x2
196 msr tpidr_el1, x3
197 msr mair_el1, x4
198 msr sp_el1, x5
199 msr vbar_el1, x6
200 msr tpidr_el0, x7
201 msr tpidrro_el0, x8
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/common/aarch64/
H A Dtegra_helpers.S79 msr CORTEX_A57_L2ECTLR_EL1, x0
86 msr CORTEX_A57_ECTLR_EL1, x0
96 msr actlr_el3, x0
100 msr actlr_el2, x0
113 msr pmintenclr_el1, x0
114 msr pmuserenr_el0, x1 // enable user mode access
124 msr cntkctl_el1, x0
338 msr CORTEX_A57_CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
347 msr CORTEX_A57_CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
368 msr oslar_el1, x0 /* os lock stays 0 across warm reset */
[all …]
/rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rdaspen/ras/
H A Drdaspen_ras_helpers.S20 msr ERXPFGCTL_EL1, xzr
29 msr ERXPFGCDN_EL1, xzr
38 msr ERXMISC0_EL1, xzr
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/aarch64/
H A Dnvg_helpers.S16 msr s3_0_c15_c1_2, x0
17 msr s3_0_c15_c1_3, x1
23 msr s3_0_c15_c1_2, x0

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