Lines Matching refs:msr
34 msr NEOVERSE_V1_CPUPSELR_EL3, x0
36 msr NEOVERSE_V1_CPUPOR_EL3, x0
38 msr NEOVERSE_V1_CPUPMR_EL3, x0
40 msr NEOVERSE_V1_CPUPCR_EL3, x0
44 msr NEOVERSE_V1_CPUPSELR_EL3, x0
46 msr NEOVERSE_V1_CPUPOR_EL3, x0
48 msr NEOVERSE_V1_CPUPMR_EL3, x0
50 msr NEOVERSE_V1_CPUPCR_EL3, x0
54 msr NEOVERSE_V1_CPUPSELR_EL3, x0
56 msr NEOVERSE_V1_CPUPOR_EL3, x0
58 msr NEOVERSE_V1_CPUPMR_EL3, x0
60 msr NEOVERSE_V1_CPUPCR_EL3, x0
64 msr NEOVERSE_V1_CPUPSELR_EL3, x0
66 msr NEOVERSE_V1_CPUPOR_EL3, x0
68 msr NEOVERSE_V1_CPUPMR_EL3, x0
70 msr NEOVERSE_V1_CPUPCR_EL3, x0
74 msr NEOVERSE_V1_CPUPSELR_EL3, x0
76 msr NEOVERSE_V1_CPUPOR_EL3, x0
78 msr NEOVERSE_V1_CPUPMR_EL3, x0
80 msr NEOVERSE_V1_CPUPCR_EL3, x0
116 msr S3_6_C15_C8_0, x0
118 msr S3_6_C15_C8_2, x0
120 msr S3_6_C15_C8_3, x0
122 msr S3_6_C15_C8_1, x0
125 msr S3_6_C15_C8_0, x0
127 msr S3_6_C15_C8_2, x0
129 msr S3_6_C15_C8_3, x0
131 msr S3_6_C15_C8_1, x0
134 msr S3_6_C15_C8_0, x0
136 msr S3_6_C15_C8_2, x0
138 msr S3_6_C15_C8_3, x0
140 msr S3_6_C15_C8_1, x0
148 msr S3_6_C15_C8_0, x0
150 msr S3_6_C15_C8_2, x0
152 msr S3_6_C15_C8_3, x0
154 msr S3_6_C15_C8_1, x0
161 msr S3_6_C15_C8_0, x0
163 msr S3_6_C15_C8_2, x0
165 msr S3_6_C15_C8_3, x0
167 msr S3_6_C15_C8_1, x0
174 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
176 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
178 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
180 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
264 msr SSBS, xzr