1*7dae0451SMin Yao Ng/* 2*7dae0451SMin Yao Ng * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3*7dae0451SMin Yao Ng * 4*7dae0451SMin Yao Ng * SPDX-License-Identifier: BSD-3-Clause 5*7dae0451SMin Yao Ng */ 6*7dae0451SMin Yao Ng 7*7dae0451SMin Yao Ng#include <arch.h> 8*7dae0451SMin Yao Ng#include <asm_macros.S> 9*7dae0451SMin Yao Ng#include <c1_premium.h> 10*7dae0451SMin Yao Ng#include <common/bl_common.h> 11*7dae0451SMin Yao Ng#include <cpu_macros.S> 12*7dae0451SMin Yao Ng 13*7dae0451SMin Yao Ng#include <plat_macros.S> 14*7dae0451SMin Yao Ng 15*7dae0451SMin Yao Ng/* Hardware handled coherency */ 16*7dae0451SMin Yao Ng#if HW_ASSISTED_COHERENCY == 0 17*7dae0451SMin Yao Ng#error "Arm C1-Premium must be compiled with HW_ASSISTED_COHERENCY enabled" 18*7dae0451SMin Yao Ng#endif 19*7dae0451SMin Yao Ng 20*7dae0451SMin Yao Ng/* 64-bit only core */ 21*7dae0451SMin Yao Ng#if CTX_INCLUDE_AARCH32_REGS == 1 22*7dae0451SMin Yao Ng#error "Arm C1-Premium supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23*7dae0451SMin Yao Ng#endif 24*7dae0451SMin Yao Ng 25*7dae0451SMin Yao Ng#if ERRATA_SME_POWER_DOWN == 0 26*7dae0451SMin Yao Ng#error "Arm C1-Premium needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27*7dae0451SMin Yao Ng#endif 28*7dae0451SMin Yao Ng 29*7dae0451SMin Yao Ngcpu_reset_prologue c1_premium 30*7dae0451SMin Yao Ng 31*7dae0451SMin Yao Ngcpu_reset_func_start c1_premium 32*7dae0451SMin Yao Ng /* Disable speculative loads */ 33*7dae0451SMin Yao Ng msr SSBS, xzr 34*7dae0451SMin Yao Ng enable_mpmm 35*7dae0451SMin Yao Ngcpu_reset_func_end c1_premium 36*7dae0451SMin Yao Ng 37*7dae0451SMin Yao Ngfunc c1_premium_core_pwr_dwn 38*7dae0451SMin Yao Ng /* --------------------------------------------------- 39*7dae0451SMin Yao Ng * Flip CPU power down bit in power control register. 40*7dae0451SMin Yao Ng * It will be set on powerdown and cleared on wakeup. 41*7dae0451SMin Yao Ng * --------------------------------------------------- 42*7dae0451SMin Yao Ng */ 43*7dae0451SMin Yao Ng sysreg_bit_toggle C1_PREMIUM_IMP_CPUPWRCTLR_EL1, \ 44*7dae0451SMin Yao Ng C1_PREMIUM_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 45*7dae0451SMin Yao Ng isb 46*7dae0451SMin Yao Ng signal_pabandon_handled 47*7dae0451SMin Yao Ng ret 48*7dae0451SMin Yao Ngendfunc c1_premium_core_pwr_dwn 49*7dae0451SMin Yao Ng 50*7dae0451SMin Yao Ng.section .rodata.c1_premium_regs, "aS" 51*7dae0451SMin Yao Ngc1_premium_regs: /* The ASCII list of register names to be reported */ 52*7dae0451SMin Yao Ng .asciz "cpuectlr_el1", "" 53*7dae0451SMin Yao Ng 54*7dae0451SMin Yao Ngfunc c1_premium_cpu_reg_dump 55*7dae0451SMin Yao Ng adr x6, c1_premium_regs 56*7dae0451SMin Yao Ng mrs x8, C1_PREMIUM_IMP_CPUECTLR_EL1 57*7dae0451SMin Yao Ng ret 58*7dae0451SMin Yao Ngendfunc c1_premium_cpu_reg_dump 59*7dae0451SMin Yao Ng 60*7dae0451SMin Yao Ngdeclare_cpu_ops c1_premium, C1_PREMIUM_MIDR, \ 61*7dae0451SMin Yao Ng c1_premium_reset_func, \ 62*7dae0451SMin Yao Ng c1_premium_core_pwr_dwn 63