1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_nano.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Nano must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Nano supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "Arm C1-Nano needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue c1_nano 30 31cpu_reset_func_start c1_nano 32 /* ---------------------------------------------------- 33 * Disable speculative loads 34 * ---------------------------------------------------- 35 */ 36 msr SSBS, xzr 37 /* model bug: not cleared on reset */ 38 sysreg_bit_clear C1_NANO_IMP_CPUPWRCTLR_EL1, \ 39 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 40 enable_mpmm 41cpu_reset_func_end c1_nano 42 43func c1_nano_core_pwr_dwn 44 /* --------------------------------------------------- 45 * Enable CPU power down bit in power control register 46 * --------------------------------------------------- 47 */ 48 sysreg_bit_toggle C1_NANO_IMP_CPUPWRCTLR_EL1, \ 49 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 50 isb 51 signal_pabandon_handled 52 ret 53endfunc c1_nano_core_pwr_dwn 54 55.section .rodata.c1_nano_regs, "aS" 56c1_nano_regs: /* The ASCII list of register names to be reported */ 57 .asciz "cpuectlr_el1", "" 58 59func c1_nano_cpu_reg_dump 60 adr x6, c1_nano_regs 61 mrs x8, C1_NANO_IMP_CPUECTLR_EL1 62 ret 63endfunc c1_nano_cpu_reg_dump 64 65declare_cpu_ops c1_nano, C1_NANO_MIDR, \ 66 c1_nano_reset_func, \ 67 c1_nano_core_pwr_dwn 68