17dae0451SMin Yao Ng/* 27dae0451SMin Yao Ng * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 37dae0451SMin Yao Ng * 47dae0451SMin Yao Ng * SPDX-License-Identifier: BSD-3-Clause 57dae0451SMin Yao Ng */ 67dae0451SMin Yao Ng 77dae0451SMin Yao Ng#include <arch.h> 87dae0451SMin Yao Ng#include <asm_macros.S> 97dae0451SMin Yao Ng#include <c1_nano.h> 107dae0451SMin Yao Ng#include <common/bl_common.h> 117dae0451SMin Yao Ng#include <cpu_macros.S> 127dae0451SMin Yao Ng 137dae0451SMin Yao Ng#include <plat_macros.S> 147dae0451SMin Yao Ng 157dae0451SMin Yao Ng/* Hardware handled coherency */ 167dae0451SMin Yao Ng#if HW_ASSISTED_COHERENCY == 0 177dae0451SMin Yao Ng#error "Arm C1-Nano must be compiled with HW_ASSISTED_COHERENCY enabled" 187dae0451SMin Yao Ng#endif 197dae0451SMin Yao Ng 207dae0451SMin Yao Ng/* 64-bit only core */ 217dae0451SMin Yao Ng#if CTX_INCLUDE_AARCH32_REGS == 1 227dae0451SMin Yao Ng#error "Arm C1-Nano supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 237dae0451SMin Yao Ng#endif 247dae0451SMin Yao Ng 257dae0451SMin Yao Ng#if ERRATA_SME_POWER_DOWN == 0 267dae0451SMin Yao Ng#error "Arm C1-Nano needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 277dae0451SMin Yao Ng#endif 287dae0451SMin Yao Ng 297dae0451SMin Yao Ngcpu_reset_prologue c1_nano 307dae0451SMin Yao Ng 317dae0451SMin Yao Ngcpu_reset_func_start c1_nano 327dae0451SMin Yao Ng /* ---------------------------------------------------- 337dae0451SMin Yao Ng * Disable speculative loads 347dae0451SMin Yao Ng * ---------------------------------------------------- 357dae0451SMin Yao Ng */ 367dae0451SMin Yao Ng msr SSBS, xzr 37*2e1dff2dSOlivier Deprez /* model bug: not cleared on reset */ 38*2e1dff2dSOlivier Deprez sysreg_bit_clear C1_NANO_IMP_CPUPWRCTLR_EL1, \ 39*2e1dff2dSOlivier Deprez C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 407dae0451SMin Yao Ng enable_mpmm 417dae0451SMin Yao Ngcpu_reset_func_end c1_nano 427dae0451SMin Yao Ng 437dae0451SMin Yao Ngfunc c1_nano_core_pwr_dwn 447dae0451SMin Yao Ng /* --------------------------------------------------- 457dae0451SMin Yao Ng * Enable CPU power down bit in power control register 467dae0451SMin Yao Ng * --------------------------------------------------- 477dae0451SMin Yao Ng */ 48*2e1dff2dSOlivier Deprez sysreg_bit_toggle C1_NANO_IMP_CPUPWRCTLR_EL1, \ 497dae0451SMin Yao Ng C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 507dae0451SMin Yao Ng isb 51*2e1dff2dSOlivier Deprez signal_pabandon_handled 527dae0451SMin Yao Ng ret 537dae0451SMin Yao Ngendfunc c1_nano_core_pwr_dwn 547dae0451SMin Yao Ng 557dae0451SMin Yao Ng.section .rodata.c1_nano_regs, "aS" 567dae0451SMin Yao Ngc1_nano_regs: /* The ASCII list of register names to be reported */ 577dae0451SMin Yao Ng .asciz "cpuectlr_el1", "" 587dae0451SMin Yao Ng 597dae0451SMin Yao Ngfunc c1_nano_cpu_reg_dump 607dae0451SMin Yao Ng adr x6, c1_nano_regs 617dae0451SMin Yao Ng mrs x8, C1_NANO_IMP_CPUECTLR_EL1 627dae0451SMin Yao Ng ret 637dae0451SMin Yao Ngendfunc c1_nano_cpu_reg_dump 647dae0451SMin Yao Ng 657dae0451SMin Yao Ngdeclare_cpu_ops c1_nano, C1_NANO_MIDR, \ 667dae0451SMin Yao Ng c1_nano_reset_func, \ 677dae0451SMin Yao Ng c1_nano_core_pwr_dwn 68