1*7dae0451SMin Yao Ng/* 2*7dae0451SMin Yao Ng * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3*7dae0451SMin Yao Ng * 4*7dae0451SMin Yao Ng * SPDX-License-Identifier: BSD-3-Clause 5*7dae0451SMin Yao Ng */ 6*7dae0451SMin Yao Ng 7*7dae0451SMin Yao Ng#include <arch.h> 8*7dae0451SMin Yao Ng#include <asm_macros.S> 9*7dae0451SMin Yao Ng#include <c1_ultra.h> 10*7dae0451SMin Yao Ng#include <common/bl_common.h> 11*7dae0451SMin Yao Ng#include <cpu_macros.S> 12*7dae0451SMin Yao Ng 13*7dae0451SMin Yao Ng#include <plat_macros.S> 14*7dae0451SMin Yao Ng 15*7dae0451SMin Yao Ng/* Hardware handled coherency */ 16*7dae0451SMin Yao Ng#if HW_ASSISTED_COHERENCY == 0 17*7dae0451SMin Yao Ng#error "Arm C1-Ultra must be compiled with HW_ASSISTED_COHERENCY enabled" 18*7dae0451SMin Yao Ng#endif 19*7dae0451SMin Yao Ng 20*7dae0451SMin Yao Ng/* 64-bit only core */ 21*7dae0451SMin Yao Ng#if CTX_INCLUDE_AARCH32_REGS == 1 22*7dae0451SMin Yao Ng#error "Arm C1-Ultra supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23*7dae0451SMin Yao Ng#endif 24*7dae0451SMin Yao Ng 25*7dae0451SMin Yao Ng#if ERRATA_SME_POWER_DOWN == 0 26*7dae0451SMin Yao Ng#error "Arm C1-Ultra needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27*7dae0451SMin Yao Ng#endif 28*7dae0451SMin Yao Ng 29*7dae0451SMin Yao Ngcpu_reset_prologue c1_ultra 30*7dae0451SMin Yao Ng 31*7dae0451SMin Yao Ngcpu_reset_func_start c1_ultra 32*7dae0451SMin Yao Ng /* ---------------------------------------------------- 33*7dae0451SMin Yao Ng * Disable speculative loads 34*7dae0451SMin Yao Ng * ---------------------------------------------------- 35*7dae0451SMin Yao Ng */ 36*7dae0451SMin Yao Ng msr SSBS, xzr 37*7dae0451SMin Yao Ng /* model bug: not cleared on reset */ 38*7dae0451SMin Yao Ng sysreg_bit_clear C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 39*7dae0451SMin Yao Ng C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 40*7dae0451SMin Yao Ng enable_mpmm 41*7dae0451SMin Yao Ngcpu_reset_func_end c1_ultra 42*7dae0451SMin Yao Ng 43*7dae0451SMin Yao Ngfunc c1_ultra_core_pwr_dwn 44*7dae0451SMin Yao Ng /* --------------------------------------------------- 45*7dae0451SMin Yao Ng * Flip CPU power down bit in power control register. 46*7dae0451SMin Yao Ng * It will be set on powerdown and cleared on wakeup 47*7dae0451SMin Yao Ng * --------------------------------------------------- 48*7dae0451SMin Yao Ng */ 49*7dae0451SMin Yao Ng sysreg_bit_toggle C1_ULTRA_IMP_CPUPWRCTLR_EL1, \ 50*7dae0451SMin Yao Ng C1_ULTRA_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 51*7dae0451SMin Yao Ng isb 52*7dae0451SMin Yao Ng signal_pabandon_handled 53*7dae0451SMin Yao Ng ret 54*7dae0451SMin Yao Ngendfunc c1_ultra_core_pwr_dwn 55*7dae0451SMin Yao Ng 56*7dae0451SMin Yao Ng.section .rodata.c1_ultra_regs, "aS" 57*7dae0451SMin Yao Ngc1_ultra_regs: /* The ASCII list of register names to be reported */ 58*7dae0451SMin Yao Ng .asciz "cpuectlr_el1", "" 59*7dae0451SMin Yao Ng 60*7dae0451SMin Yao Ngfunc c1_ultra_cpu_reg_dump 61*7dae0451SMin Yao Ng adr x6, c1_ultra_regs 62*7dae0451SMin Yao Ng mrs x8, C1_ULTRA_IMP_CPUECTLR_EL1 63*7dae0451SMin Yao Ng ret 64*7dae0451SMin Yao Ngendfunc c1_ultra_cpu_reg_dump 65*7dae0451SMin Yao Ng 66*7dae0451SMin Yao Ngdeclare_cpu_ops c1_ultra, C1_ULTRA_MIDR, \ 67*7dae0451SMin Yao Ng c1_ultra_reset_func, \ 68*7dae0451SMin Yao Ng c1_ultra_core_pwr_dwn 69