Home
last modified time | relevance | path

Searched refs:mapping (Results 1 – 25 of 31) sorted by relevance

12

/rk3399_ARM-atf/services/std_svc/sdei/
H A Dsdei_event.c24 const sdei_mapping_t *mapping; in get_event_entry() local
34 mapping = SDEI_PRIVATE_MAPPING(); in get_event_entry()
35 idx = MAP_OFF(map, mapping); in get_event_entry()
38 base_idx = plat_my_core_pos() * ((unsigned int) mapping->num_maps); in get_event_entry()
47 mapping = SDEI_SHARED_MAPPING(); in get_event_entry()
48 idx = MAP_OFF(map, mapping); in get_event_entry()
105 const sdei_mapping_t *mapping; in find_event_map_by_intr() local
114 mapping = shared ? SDEI_SHARED_MAPPING() : SDEI_PRIVATE_MAPPING(); in find_event_map_by_intr()
115 iterate_mapping(mapping, i, map) { in find_event_map_by_intr()
129 const sdei_mapping_t *mapping; in find_event_map() local
[all …]
H A Dsdei_main.c865 const sdei_mapping_t *mapping; in sdei_shared_reset() local
889 for_each_mapping_type(i, mapping) { in sdei_shared_reset()
890 iterate_mapping(mapping, j, map) { in sdei_shared_reset()
/rk3399_ARM-atf/docs/plat/
H A Dimx8m.rst83 There is a special case of mapping the DRAM: entire DRAM available on the
86 Mapping the entire DRAM allows the usage of 2MB block mapping in Level-2
88 Level-3 PTE mapping is used instead then additional PTEs would be required,
92 family it should rather be avoided creating additional Level-3 mapping and
93 introduce more PTEs, hence the implementation uses Level-2 mapping which
96 The reason for the MT_RW attribute mapping scheme is the fact that the SMC
102 Therefore, DRAM mapping is done with MT_RW attributes, as it is required for
H A Dallwinner.rst101 The mapping we use on those SoCs is as follows:
133 SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
/rk3399_ARM-atf/docs/components/
H A Dxlat-tables-lib-v2-design.rst19 #. Support for dynamic mapping and unmapping of regions, even while the MMU is
35 support dynamic mapping. Although potential bug fixes will be applied to both
63 - its mapping granularity (optional).
79 The granularity controls the translation table level to go down to when mapping
86 contains 512 entries, each mapping 4KB).
97 then they might enforce a 4KB mapping granularity for this 2MB region from the
102 library will choose the mapping granularity for this region as it sees fit (more
103 details can be found in `The memory mapping algorithm`_ section below).
171 The library optionally supports dynamic memory mapping. This feature may be
174 When dynamic memory mapping is enabled, the library categorises mmap regions as
[all …]
H A Dgranule-protection-tables-design.rst50 mapping is used. Level 0 entry can also link to a level 1 table (GPT Table
51 descriptor) with a 2 step mapping. To change PAS of a region dynamically, the
106 #. The desired attributes of this memory region (mapping type, PAS type)
119 imply, ``GPT_MAP_REGION_BLOCK`` creates a region using only L0 mapping while
H A Dnuma-per-cpu.rst187 The platform is free to maintain this mapping however it prefers, and may do so
194 page-aligned bases and sizes for page table mapping through the xlat library,
H A Dffa-manifest-binding.rst38 - These 4 <u32> values are packed similar to the UUID register mapping
H A Drmm-el3-comms-spec.rst1311 BDF Mapping Info structure contains information about each Device-Bus-Function (BDF) mapping
1317 | mapping_base | 0 | uint16_t | Base of BDF mapping (inclusive) |
1319 | mapping_top | 2 | uint16_t | Top of BDF mapping (exclusive) |
/rk3399_ARM-atf/lib/romlib/
H A Dromlib_generator.py99 def build_template(self, name, mapping=None, remove_comment=False): argument
120 return template.substitute(mapping)
268 mapping = {"jmptbl_address": matching_symbol.group(1)}
271 output_file.write(self.build_template("jmptbl_glob_var.S", mapping))
/rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/
H A Ddimm.c234 if (spd->mapping[i] == udimm_rc_e_dq[i]) { in cal_dimm_params()
238 ptr = (unsigned char *)&spd->mapping[i]; in cal_dimm_params()
391 pdimm->dq_mapping[i] = spd->mapping[i]; in cal_dimm_params()
395 pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0; in cal_dimm_params()
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-3.rst31 mapping specifying both ``MT_RO`` and ``MT_EXECUTE_NEVER`` should result in a
49 would only manifest itself for device memory mapped as RO; use of this mapping
50 is considered rare, although the upstream QEMU platform uses this mapping when
/rk3399_ARM-atf/include/drivers/nxp/ddr/
H A Ddimm.h93 unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ member
/rk3399_ARM-atf/plat/nxp/soc-ls1028a/
H A Dsoc.def79 # Enable dynamic memory mapping
/rk3399_ARM-atf/fdts/
H A Dstm32mp13-ddr3-1x4Gb-1066-binF.dtsi16 * address mapping : RBC
H A Dstm32mp15-ddr3-2x4Gb-1066-binG.dtsi13 * Address mapping type: RBC
H A Dstm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi15 * address mapping : RBC
H A Dstm32mp15-ddr3-1x4Gb-1066-binG.dtsi13 * Address mapping type: RBC
H A Dstm32mp15-ddr3-1x2Gb-1066-binG.dtsi13 * Address mapping type: RBC
/rk3399_ARM-atf/plat/nxp/soc-ls1043a/
H A Dsoc.def88 # enable dynamic memory mapping
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/
H A Dsoc.def88 # enable dynamic memory mapping
/rk3399_ARM-atf/plat/nxp/soc-lx2160a/
H A Dsoc.def115 # enable dynamic memory mapping
/rk3399_ARM-atf/docs/plat/st/
H A Dstm32mp2.rst68 Memory mapping
H A Dstm32mp1.rst49 Memory mapping
/rk3399_ARM-atf/docs/plat/marvell/armada/
H A Dporting.rst26 This file describes the SoC physical memory mapping to be used for the CCU,

12