xref: /rk3399_ARM-atf/docs/plat/marvell/armada/porting.rst (revision 8f09da46e263cdb97f01edce449aa5b769cca2f5)
1a2847172SGrzegorz JaszczykTF-A Porting Guide for Marvell Platforms
2a2847172SGrzegorz Jaszczyk========================================
3a2847172SGrzegorz Jaszczyk
4a2847172SGrzegorz JaszczykThis section describes how to port TF-A to a customer board, assuming that the
5a2847172SGrzegorz JaszczykSoC being used is already supported in TF-A.
6a2847172SGrzegorz Jaszczyk
7a2847172SGrzegorz Jaszczyk
8a2847172SGrzegorz JaszczykSource Code Structure
9a2847172SGrzegorz Jaszczyk---------------------
10a2847172SGrzegorz Jaszczyk
11a2847172SGrzegorz Jaszczyk- The customer platform specific code shall reside under ``plat/marvell/armada/<soc family>/<soc>_cust``
12a2847172SGrzegorz Jaszczyk  (e.g. 'plat/marvell/armada/a8k/a7040_cust').
13a2847172SGrzegorz Jaszczyk- The platform name for build purposes is called ``<soc>_cust`` (e.g. ``a7040_cust``).
14a2847172SGrzegorz Jaszczyk- The build system will reuse all files from within the soc directory, and take only the porting
15a2847172SGrzegorz Jaszczyk  files from the customer platform directory.
16a2847172SGrzegorz Jaszczyk
17a2847172SGrzegorz JaszczykFiles that require porting are located at ``plat/marvell/armada/<soc family>/<soc>_cust`` directory.
18a2847172SGrzegorz Jaszczyk
19a2847172SGrzegorz Jaszczyk
20a2847172SGrzegorz JaszczykArmada-70x0/Armada-80x0 Porting
21a2847172SGrzegorz Jaszczyk-------------------------------
22a2847172SGrzegorz Jaszczyk
23a2847172SGrzegorz JaszczykSoC Physical Address Map (marvell_plat_config.c)
24a2847172SGrzegorz Jaszczyk~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
25a2847172SGrzegorz Jaszczyk
26a2847172SGrzegorz JaszczykThis file describes the SoC physical memory mapping to be used for the CCU,
27a2847172SGrzegorz JaszczykIOWIN, AXI-MBUS and IOB address decode units (Refer to the functional spec for
28a2847172SGrzegorz Jaszczykmore details).
29a2847172SGrzegorz Jaszczyk
30a2847172SGrzegorz JaszczykIn most cases, using the default address decode windows should work OK.
31a2847172SGrzegorz Jaszczyk
32a2847172SGrzegorz JaszczykIn cases where a special physical address map is needed (e.g. Special size for
33a2847172SGrzegorz JaszczykPCIe MEM windows, large memory mapped SPI flash...), then porting of the SoC
34a2847172SGrzegorz Jaszczykmemory map is required.
35a2847172SGrzegorz Jaszczyk
36a2847172SGrzegorz Jaszczyk.. note::
37a2847172SGrzegorz Jaszczyk   For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please
38a2847172SGrzegorz Jaszczyk   refer to the SoC functional spec, and under
39*663f6bcfSGrzegorz Jaszczyk   ``docs/plat/marvell/armada/misc/mvebu-[ccu/iob/amb/io-win].rst`` files.
40a2847172SGrzegorz Jaszczyk
41a2847172SGrzegorz Jaszczykboot loader recovery (marvell_plat_config.c)
42a2847172SGrzegorz Jaszczyk~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
43a2847172SGrzegorz Jaszczyk
44a2847172SGrzegorz Jaszczyk- Background:
45a2847172SGrzegorz Jaszczyk
46a2847172SGrzegorz Jaszczyk  Boot rom can skip the current image and choose to boot from next position if a
47a2847172SGrzegorz Jaszczyk  specific value (``0xDEADB002``) is returned by the ble main function. This
48a2847172SGrzegorz Jaszczyk  feature is used for boot loader recovery by booting from a valid flash-image
49a2847172SGrzegorz Jaszczyk  saved in next position on flash (e.g. address 2M in SPI flash).
50a2847172SGrzegorz Jaszczyk
51a2847172SGrzegorz Jaszczyk  Supported options to implement the skip request are:
52a2847172SGrzegorz Jaszczyk    - GPIO
53a2847172SGrzegorz Jaszczyk    - I2C
54a2847172SGrzegorz Jaszczyk    - User defined
55a2847172SGrzegorz Jaszczyk
56a2847172SGrzegorz Jaszczyk- Porting:
57a2847172SGrzegorz Jaszczyk
58a2847172SGrzegorz Jaszczyk  Under marvell_plat_config.c, implement struct skip_image that includes
59a2847172SGrzegorz Jaszczyk  specific board parameters.
60a2847172SGrzegorz Jaszczyk
61a2847172SGrzegorz Jaszczyk  .. warning::
62a2847172SGrzegorz Jaszczyk     To disable this feature make sure the struct skip_image is not implemented.
63a2847172SGrzegorz Jaszczyk
64a2847172SGrzegorz Jaszczyk- Example:
65a2847172SGrzegorz Jaszczyk
66a2847172SGrzegorz JaszczykIn A7040-DB specific implementation
67a2847172SGrzegorz Jaszczyk(``plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c``), the image skip is
68a2847172SGrzegorz Jaszczykimplemented using GPIO: mpp 33 (SW5).
69a2847172SGrzegorz Jaszczyk
70a2847172SGrzegorz JaszczykBefore resetting the board make sure there is a valid image on the next flash
71a2847172SGrzegorz Jaszczykaddress:
72a2847172SGrzegorz Jaszczyk
73a2847172SGrzegorz Jaszczyk -tftp [valid address] flash-image.bin
74a2847172SGrzegorz Jaszczyk -sf update [valid address] 0x2000000 [size]
75a2847172SGrzegorz Jaszczyk
76a2847172SGrzegorz JaszczykPress reset and keep pressing the button connected to the chosen GPIO pin. A
77a2847172SGrzegorz Jaszczykskip image request message is printed on the screen and boot rom boots from the
78a2847172SGrzegorz Jaszczyksaved image at the next position.
79a2847172SGrzegorz Jaszczyk
80a2847172SGrzegorz JaszczykDDR Porting (dram_port.c)
81a2847172SGrzegorz Jaszczyk~~~~~~~~~~~~~~~~~~~~~~~~~
82a2847172SGrzegorz Jaszczyk
83a2847172SGrzegorz JaszczykThis file defines the dram topology and parameters of the target board.
84a2847172SGrzegorz Jaszczyk
85a2847172SGrzegorz JaszczykThe DDR code is part of the BLE component, which is an extension of ARM Trusted
86a2847172SGrzegorz JaszczykFirmware (TF-A).
87a2847172SGrzegorz Jaszczyk
88a2847172SGrzegorz JaszczykThe DDR driver called mv_ddr is released separately apart from TF-A sources.
89a2847172SGrzegorz Jaszczyk
90a2847172SGrzegorz JaszczykThe BLE and consequently, the DDR init code is executed at the early stage of
91a2847172SGrzegorz Jaszczykthe boot process.
92a2847172SGrzegorz Jaszczyk
93a2847172SGrzegorz JaszczykEach supported platform of the TF-A has its own DDR porting file called
94a2847172SGrzegorz Jaszczykdram_port.c located at ``atf/plat/marvell/armada/a8k/<platform>/board`` directory.
95a2847172SGrzegorz Jaszczyk
96a2847172SGrzegorz JaszczykPlease refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed
97a2847172SGrzegorz Jaszczykporting description.
98a2847172SGrzegorz Jaszczyk
99a2847172SGrzegorz JaszczykThe build target directory is "build/<platform>/release/ble".
100a2847172SGrzegorz Jaszczyk
101a2847172SGrzegorz JaszczykComphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
102a2847172SGrzegorz Jaszczyk~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
103a2847172SGrzegorz Jaszczyk
104a2847172SGrzegorz Jaszczyk- Background:
105a2847172SGrzegorz Jaszczyk    Some of the comphy's parameters value depend on the HW connection between
106a2847172SGrzegorz Jaszczyk    the SoC and the PHY. Every board type has specific HW characteristics like
107a2847172SGrzegorz Jaszczyk    wire length. Due to those differences some comphy parameters vary between
108a2847172SGrzegorz Jaszczyk    board types. Therefore each board type can have its own list of values for
109a2847172SGrzegorz Jaszczyk    all relevant comphy parameters. The PHY porting layer specifies which
110a2847172SGrzegorz Jaszczyk    parameters need to be suited and the board designer should provide relevant
111a2847172SGrzegorz Jaszczyk    values.
112a2847172SGrzegorz Jaszczyk
113a2847172SGrzegorz Jaszczyk    The PHY porting layer simplifies updating static values per board type,
114a2847172SGrzegorz Jaszczyk    which are now grouped in one place.
115a2847172SGrzegorz Jaszczyk
116a2847172SGrzegorz Jaszczyk    .. note::
117a2847172SGrzegorz Jaszczyk        The parameters for the same type of comphy may vary even for the same
118a2847172SGrzegorz Jaszczyk        board type, it is because the lanes from comphy-x to some PHY may have
119a2847172SGrzegorz Jaszczyk        different HW characteristic than lanes from comphy-y to the same
120a2847172SGrzegorz Jaszczyk        (multiplexed) or other PHY.
121a2847172SGrzegorz Jaszczyk
122a2847172SGrzegorz Jaszczyk- Porting:
123a2847172SGrzegorz Jaszczyk    The porting layer for PHY was introduced in TF-A. There is one file
124a2847172SGrzegorz Jaszczyk    ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the
125a2847172SGrzegorz Jaszczyk    defaults. Those default parameters are used only if there is no appropriate
126a2847172SGrzegorz Jaszczyk    phy-porting-layer.h file under: ``plat/marvell/armada/<soc
127a2847172SGrzegorz Jaszczyk    family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h
128a2847172SGrzegorz Jaszczyk    exists, the phy-default-porting-layer.h is not going to be included.
129a2847172SGrzegorz Jaszczyk
130a2847172SGrzegorz Jaszczyk    .. warning::
131a2847172SGrzegorz Jaszczyk        Not all comphy types are already reworked to support the PHY porting
132a2847172SGrzegorz Jaszczyk        layer, currently the porting layer is supported for XFI/SFI and SATA
133a2847172SGrzegorz Jaszczyk        comphy types.
134a2847172SGrzegorz Jaszczyk
135a2847172SGrzegorz Jaszczyk    The easiest way to prepare the PHY porting layer for custom board is to copy
136a2847172SGrzegorz Jaszczyk    existing example to a new platform:
137a2847172SGrzegorz Jaszczyk
138a2847172SGrzegorz Jaszczyk    - cp ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/armada/<soc family>/<platform>/board/phy-porting-layer.h"
139a2847172SGrzegorz Jaszczyk    - adjust relevant parameters or
140a2847172SGrzegorz Jaszczyk    - if different comphy index is used for specific feature, move it to proper table entry and then adjust.
141a2847172SGrzegorz Jaszczyk
142a2847172SGrzegorz Jaszczyk    .. note::
143a2847172SGrzegorz Jaszczyk        The final table size with comphy parameters can be different, depending
144a2847172SGrzegorz Jaszczyk        on the CP module count for given SoC type.
145a2847172SGrzegorz Jaszczyk
146a2847172SGrzegorz Jaszczyk- Example:
147a2847172SGrzegorz Jaszczyk    Example porting layer for armada-8040-db is under:
148a2847172SGrzegorz Jaszczyk    ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h``
149a2847172SGrzegorz Jaszczyk
150a2847172SGrzegorz Jaszczyk    .. note::
151a2847172SGrzegorz Jaszczyk        If there is no PHY porting layer for new platform (missing
152a2847172SGrzegorz Jaszczyk        phy-porting-layer.h), the default values are used
153a2847172SGrzegorz Jaszczyk        (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is
154a2847172SGrzegorz Jaszczyk        warned:
155a2847172SGrzegorz Jaszczyk
156a2847172SGrzegorz Jaszczyk    .. warning::
157a2847172SGrzegorz Jaszczyk        "Using default comphy parameters - it may be required to suit them for
158a2847172SGrzegorz Jaszczyk        your board".
159