Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinne

Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinner): add extra CPU control registers
refactor(allwinner): consolidate sunxi_cfg.h files

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feat(allwinner): add support for Allwinner T507 SoC

The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision

feat(allwinner): add support for Allwinner T507 SoC

The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision out there, which uses a different CPU cluster control block.
The same die revision has been spotted in some, but not all, H313 SoCs.

Apart from that IP block, the rest of the SoC seems the same, so we can
support them using the existing H616 port. The die revision can be
auto-detected, so there is no extra build option or knowledge needed.

Provide the deviating CPU power up/down sequence for the die variant.
The new IP block uses per-core instead of per-cluster registers, but
follows the same pattern otherwise.

Since the CPU ops code is shared among all Allwinner SoCs, we need to
dummy-define the new register names for the older SoCs. The actual new
code is guarded by a predicate function, that is hard coded to return
true on the other SoCs. Since this is a static inline function in a
header file, the compiler will optimise away the unneeded branch there,
so the generated code for the other SoCs stays the same.

Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes Icf5e3045,Ie5fb0b72 into integration

* changes:
docs(allwinner): update SoC list and build options
docs(allwinner): add SUNXI_SETUP_REGULATORS build option

docs(allwinner): update SoC list and build options

Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to t

docs(allwinner): update SoC list and build options

Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to the build target names.
Also add some explanation about the recently introduced PSCI power
management providers.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icf5e304562c3082552bf08d7b26904caf9074936

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docs(allwinner): add SUNXI_SETUP_REGULATORS build option

Document the newly introduced SUNXI_SETUP_REGULATORS build option, that
allows to disable PMIC regulator setup at build time.

Signed-off-by:

docs(allwinner): add SUNXI_SETUP_REGULATORS build option

Document the newly introduced SUNXI_SETUP_REGULATORS build option, that
allows to disable PMIC regulator setup at build time.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie5fb0b7220426b67cfffc95df4cabb31a6ec174a

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Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
all

Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
allwinner: Express memmap more dynamically
allwinner: Move sunxi_cpu_power_off_self() into platforms
allwinner: Move SEPARATE_NOBITS_REGION to platforms
doc: allwinner: Reorder sections, document memory mapping

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allwinner: Add Allwinner H616 SoC support

The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DR

allwinner: Add Allwinner H616 SoC support

The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.

The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.

Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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doc: allwinner: Reorder sections, document memory mapping

Update the Allwinner platform documentation.
Reorder the section, to have the build instructions first, followed by
hints about the installa

doc: allwinner: Reorder sections, document memory mapping

Update the Allwinner platform documentation.
Reorder the section, to have the build instructions first, followed by
hints about the installation.

Add some ASCII art about the layout of our virtual memory map, which
uses a non-trivial condensed virtual address space.

Change-Id: Iaaa79b4366012394e15e4c1b26c212b5efb6ed6a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "doc: Fix some broken links" into integration

doc: Fix some broken links

Fix all external broken links reported by Sphinx linkcheck tool.

This does not take care of broken cross-references between internal
TF-A documentation files. These will

doc: Fix some broken links

Fix all external broken links reported by Sphinx linkcheck tool.

This does not take care of broken cross-references between internal
TF-A documentation files. These will be fixed in a future patch.

Change-Id: I2a740a3ec0b688c14aad575a6c2ac71e72ce051e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge "Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain"" into integration

Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain"

This reverts commit de9bf1d8a2de952bfc17cdf7082b41f9c185e54d.

Change-Id: Iebb6297ce290a10ee850bf6a9c71e7eb530b085f

Merge "GCC: Upgrade to version 9.2-2019.12 of toolchain" into integration

GCC: Upgrade to version 9.2-2019.12 of toolchain

This toolchain provides multiple cross compilers and are publicly
available on www.developer.arm.com

We thoroughly test TF-A in CI using:
AArch32 ba

GCC: Upgrade to version 9.2-2019.12 of toolchain

This toolchain provides multiple cross compilers and are publicly
available on www.developer.arm.com

We thoroughly test TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I2360a3ac6705c68dca781b85e9894867df255b3e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "pb/sphinx-doc" into integration

* changes:
doc: Use proper note and warning annotations
doc: Refactor contributor acknowledgements
doc: Reorganise images and update l

Merge changes from topic "pb/sphinx-doc" into integration

* changes:
doc: Use proper note and warning annotations
doc: Refactor contributor acknowledgements
doc: Reorganise images and update links
doc: Set correct syntax highlighting style
doc: Add minimal glossary
doc: Remove per-page contents lists
doc: Make checkpatch ignore rst files
doc: Format security advisory titles and headings
doc: Reformat platform port documents
doc: Normalise section numbering and headings
doc: Reword document titles

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doc: Set correct syntax highlighting style

Several code blocks do not specify a language for syntax
highlighting. This results in Sphinx using a default highlighter
which is Python.

This patch adds

doc: Set correct syntax highlighting style

Several code blocks do not specify a language for syntax
highlighting. This results in Sphinx using a default highlighter
which is Python.

This patch adds the correct language to each code block that doesn't
already specify it.

Change-Id: Icce1949aabfdc11a334a42d49edf55fa673cddc3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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doc: Reformat platform port documents

The platform port documents are not very standardised right now and
they don't integrate properly into the document tree so:

1) Make sure each port has a prope

doc: Reformat platform port documents

The platform port documents are not very standardised right now and
they don't integrate properly into the document tree so:

1) Make sure each port has a proper name and title (incl. owner)
2) Correct use of headings, subheadings, etc in each port
3) Resolve any naming conflicts between documents

Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

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Merge pull request #1465 from Andre-ARM/allwinner/h6-support

allwinner: Add H6 SoC support

allwinner: Add Allwinner H6 SoC support

The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

In

allwinner: Add Allwinner H6 SoC support

The H6 is Allwinner's most recent SoC. It shares most peripherals with the
other ARMv8 Allwinner SoCs (A64/H5), but has a completely different memory
map.

Introduce a separate platform target, which includes a different header
file to cater for the address differences. Also add the new build target
to the documentation.

The new ATF platform name is "sun50i_h6".

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge pull request #1458 from Andre-ARM/allwinner/fixes

allwinner: various smaller fixes

Merge pull request #1447 from Amit-Radur/bl32_v1

allwinner: Add BL32 (corresponds to Trusted OS) support

allwinner: doc: add missing paragraphs

Add two empty lines to denote the paragraphs properly and improve
readability.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara

allwinner: doc: add missing paragraphs

Add two empty lines to denote the paragraphs properly and improve
readability.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Add BL32 (corresponds to Trusted OS) support

This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dis

allwinner: Add BL32 (corresponds to Trusted OS) support

This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS)
as an input using the 'SPD=<dispatcher name>' option during bl31 build.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>

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allwinner: Add BL32 (corresponds to Trusted OS) support

This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dis

allwinner: Add BL32 (corresponds to Trusted OS) support

This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS)
as an input using the 'SPD=<dispatcher name>' option during bl31 build.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>

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Merge pull request #1400 from Andre-ARM/allwinner/v1

Allwinner platform support