1*3812cebaSDavid Jander// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*3812cebaSDavid Jander/* 3*3812cebaSDavid Jander * Copyright (C) 2023, STMicroelectronics - All Rights Reserved 4*3812cebaSDavid Jander */ 5*3812cebaSDavid Jander 6*3812cebaSDavid Jander/* 7*3812cebaSDavid Jander * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs 8*3812cebaSDavid Jander * DDR type: DDR3 / DDR3L 9*3812cebaSDavid Jander * DDR width: 16bits 10*3812cebaSDavid Jander * DDR density: 4Gb 11*3812cebaSDavid Jander * System frequency: 533000Khz 12*3812cebaSDavid Jander * Relaxed Timing Mode: false 13*3812cebaSDavid Jander * Address mapping type: RBC 14*3812cebaSDavid Jander * 15*3812cebaSDavid Jander * Save Date: 2020.02.20, save Time: 18:45:20 16*3812cebaSDavid Jander */ 17*3812cebaSDavid Jander 18*3812cebaSDavid Jander#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" 19*3812cebaSDavid Jander#define DDR_MEM_SPEED 533000 20*3812cebaSDavid Jander#define DDR_MEM_SIZE 0x10000000 21*3812cebaSDavid Jander 22*3812cebaSDavid Jander#define DDR_MSTR 0x00041401 23*3812cebaSDavid Jander#define DDR_MRCTRL0 0x00000010 24*3812cebaSDavid Jander#define DDR_MRCTRL1 0x00000000 25*3812cebaSDavid Jander#define DDR_DERATEEN 0x00000000 26*3812cebaSDavid Jander#define DDR_DERATEINT 0x00800000 27*3812cebaSDavid Jander#define DDR_PWRCTL 0x00000000 28*3812cebaSDavid Jander#define DDR_PWRTMG 0x00400010 29*3812cebaSDavid Jander#define DDR_HWLPCTL 0x00000000 30*3812cebaSDavid Jander#define DDR_RFSHCTL0 0x00210000 31*3812cebaSDavid Jander#define DDR_RFSHCTL3 0x00000000 32*3812cebaSDavid Jander#define DDR_RFSHTMG 0x0040008B 33*3812cebaSDavid Jander#define DDR_CRCPARCTL0 0x00000000 34*3812cebaSDavid Jander#define DDR_DRAMTMG0 0x121B1214 35*3812cebaSDavid Jander#define DDR_DRAMTMG1 0x000A041C 36*3812cebaSDavid Jander#define DDR_DRAMTMG2 0x0608090F 37*3812cebaSDavid Jander#define DDR_DRAMTMG3 0x0050400C 38*3812cebaSDavid Jander#define DDR_DRAMTMG4 0x08040608 39*3812cebaSDavid Jander#define DDR_DRAMTMG5 0x06060403 40*3812cebaSDavid Jander#define DDR_DRAMTMG6 0x02020002 41*3812cebaSDavid Jander#define DDR_DRAMTMG7 0x00000202 42*3812cebaSDavid Jander#define DDR_DRAMTMG8 0x00001005 43*3812cebaSDavid Jander#define DDR_DRAMTMG14 0x000000A0 44*3812cebaSDavid Jander#define DDR_ZQCTL0 0xC2000040 45*3812cebaSDavid Jander#define DDR_DFITMG0 0x02060105 46*3812cebaSDavid Jander#define DDR_DFITMG1 0x00000202 47*3812cebaSDavid Jander#define DDR_DFILPCFG0 0x07000000 48*3812cebaSDavid Jander#define DDR_DFIUPD0 0xC0400003 49*3812cebaSDavid Jander#define DDR_DFIUPD1 0x00000000 50*3812cebaSDavid Jander#define DDR_DFIUPD2 0x00000000 51*3812cebaSDavid Jander#define DDR_DFIPHYMSTR 0x00000000 52*3812cebaSDavid Jander#define DDR_ODTCFG 0x06000600 53*3812cebaSDavid Jander#define DDR_ODTMAP 0x00000001 54*3812cebaSDavid Jander#define DDR_SCHED 0x00000C01 55*3812cebaSDavid Jander#define DDR_SCHED1 0x00000000 56*3812cebaSDavid Jander#define DDR_PERFHPR1 0x01000001 57*3812cebaSDavid Jander#define DDR_PERFLPR1 0x08000200 58*3812cebaSDavid Jander#define DDR_PERFWR1 0x08000400 59*3812cebaSDavid Jander#define DDR_DBG0 0x00000000 60*3812cebaSDavid Jander#define DDR_DBG1 0x00000000 61*3812cebaSDavid Jander#define DDR_DBGCMD 0x00000000 62*3812cebaSDavid Jander#define DDR_POISONCFG 0x00000000 63*3812cebaSDavid Jander#define DDR_PCCFG 0x00000010 64*3812cebaSDavid Jander#define DDR_PCFGR_0 0x00010000 65*3812cebaSDavid Jander#define DDR_PCFGW_0 0x00000000 66*3812cebaSDavid Jander#define DDR_PCFGQOS0_0 0x02100C03 67*3812cebaSDavid Jander#define DDR_PCFGQOS1_0 0x00800100 68*3812cebaSDavid Jander#define DDR_PCFGWQOS0_0 0x01100C03 69*3812cebaSDavid Jander#define DDR_PCFGWQOS1_0 0x01000200 70*3812cebaSDavid Jander#define DDR_PCFGR_1 0x00010000 71*3812cebaSDavid Jander#define DDR_PCFGW_1 0x00000000 72*3812cebaSDavid Jander#define DDR_PCFGQOS0_1 0x02100C03 73*3812cebaSDavid Jander#define DDR_PCFGQOS1_1 0x00800040 74*3812cebaSDavid Jander#define DDR_PCFGWQOS0_1 0x01100C03 75*3812cebaSDavid Jander#define DDR_PCFGWQOS1_1 0x01000200 76*3812cebaSDavid Jander#define DDR_ADDRMAP1 0x00151515 77*3812cebaSDavid Jander#define DDR_ADDRMAP2 0x00000000 78*3812cebaSDavid Jander#define DDR_ADDRMAP3 0x1F000000 79*3812cebaSDavid Jander#define DDR_ADDRMAP4 0x00001F1F 80*3812cebaSDavid Jander#define DDR_ADDRMAP5 0x03030303 81*3812cebaSDavid Jander#define DDR_ADDRMAP6 0x0F0F0303 82*3812cebaSDavid Jander#define DDR_ADDRMAP9 0x00000000 83*3812cebaSDavid Jander#define DDR_ADDRMAP10 0x00000000 84*3812cebaSDavid Jander#define DDR_ADDRMAP11 0x00000000 85*3812cebaSDavid Jander#define DDR_PGCR 0x01442E02 86*3812cebaSDavid Jander#define DDR_PTR0 0x0022AA5B 87*3812cebaSDavid Jander#define DDR_PTR1 0x04841104 88*3812cebaSDavid Jander#define DDR_PTR2 0x042DA068 89*3812cebaSDavid Jander#define DDR_ACIOCR 0x10400812 90*3812cebaSDavid Jander#define DDR_DXCCR 0x00000C40 91*3812cebaSDavid Jander#define DDR_DSGCR 0xF200011F 92*3812cebaSDavid Jander#define DDR_DCR 0x0000000B 93*3812cebaSDavid Jander#define DDR_DTPR0 0x38D488D0 94*3812cebaSDavid Jander#define DDR_DTPR1 0x098B00D8 95*3812cebaSDavid Jander#define DDR_DTPR2 0x10023600 96*3812cebaSDavid Jander#define DDR_MR0 0x00000840 97*3812cebaSDavid Jander#define DDR_MR1 0x00000000 98*3812cebaSDavid Jander#define DDR_MR2 0x00000248 99*3812cebaSDavid Jander#define DDR_MR3 0x00000000 100*3812cebaSDavid Jander#define DDR_ODTCR 0x00010000 101*3812cebaSDavid Jander#define DDR_ZQ0CR1 0x00000038 102*3812cebaSDavid Jander#define DDR_DX0GCR 0x0000CE81 103*3812cebaSDavid Jander#define DDR_DX0DLLCR 0x40000000 104*3812cebaSDavid Jander#define DDR_DX0DQTR 0xFFFFFFFF 105*3812cebaSDavid Jander#define DDR_DX0DQSTR 0x3DB02000 106*3812cebaSDavid Jander#define DDR_DX1GCR 0x0000CE81 107*3812cebaSDavid Jander#define DDR_DX1DLLCR 0x40000000 108*3812cebaSDavid Jander#define DDR_DX1DQTR 0xFFFFFFFF 109*3812cebaSDavid Jander#define DDR_DX1DQSTR 0x3DB02000 110*3812cebaSDavid Jander#define DDR_DX2GCR 0x0000CE80 111*3812cebaSDavid Jander#define DDR_DX2DLLCR 0x40000000 112*3812cebaSDavid Jander#define DDR_DX2DQTR 0xFFFFFFFF 113*3812cebaSDavid Jander#define DDR_DX2DQSTR 0x3DB02000 114*3812cebaSDavid Jander#define DDR_DX3GCR 0x0000CE80 115*3812cebaSDavid Jander#define DDR_DX3DLLCR 0x40000000 116*3812cebaSDavid Jander#define DDR_DX3DQTR 0xFFFFFFFF 117*3812cebaSDavid Jander#define DDR_DX3DQSTR 0x3DB02000 118*3812cebaSDavid Jander 119*3812cebaSDavid Jander#include "stm32mp15-ddr.dtsi" 120