1*3b0de918SJiafei Pan# 2*3b0de918SJiafei Pan# Copyright 2017-2021 NXP 3*3b0de918SJiafei Pan# 4*3b0de918SJiafei Pan# SPDX-License-Identifier: BSD-3-Clause 5*3b0de918SJiafei Pan# 6*3b0de918SJiafei Pan# 7*3b0de918SJiafei Pan#------------------------------------------------------------------------------ 8*3b0de918SJiafei Pan# 9*3b0de918SJiafei Pan# This file contains the basic architecture definitions that drive the build 10*3b0de918SJiafei Pan# 11*3b0de918SJiafei Pan# ----------------------------------------------------------------------------- 12*3b0de918SJiafei Pan 13*3b0de918SJiafei PanCORE_TYPE := a53 14*3b0de918SJiafei Pan 15*3b0de918SJiafei PanCACHE_LINE := 6 16*3b0de918SJiafei Pan 17*3b0de918SJiafei Pan# set to GIC400 or GIC500 18*3b0de918SJiafei PanGIC := GIC400 19*3b0de918SJiafei Pan 20*3b0de918SJiafei Pan# set to CCI400 or CCN504 or CCN508 21*3b0de918SJiafei PanINTERCONNECT := CCI400 22*3b0de918SJiafei Pan 23*3b0de918SJiafei Pan# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 24*3b0de918SJiafei PanCHASSIS := 2 25*3b0de918SJiafei Pan 26*3b0de918SJiafei Pan# TZC IP Details TZC used is TZC380 or TZC400 27*3b0de918SJiafei PanTZC_ID := TZC380 28*3b0de918SJiafei Pan 29*3b0de918SJiafei Pan# CONSOLE Details available is NS16550 or PL011 30*3b0de918SJiafei PanCONSOLE := NS16550 31*3b0de918SJiafei Pan 32*3b0de918SJiafei Pan# Select the DDR PHY generation to be used 33*3b0de918SJiafei PanPLAT_DDR_PHY := PHY_GEN1 34*3b0de918SJiafei Pan 35*3b0de918SJiafei PanPHYS_SYS := 64 36*3b0de918SJiafei Pan 37*3b0de918SJiafei Pan# ddr controller - set to MMDC or NXP 38*3b0de918SJiafei PanDDRCNTLR := NXP 39*3b0de918SJiafei Pan 40*3b0de918SJiafei Pan# ddr phy - set to NXP or SNPS 41*3b0de918SJiafei PanDDRPHY := NXP 42*3b0de918SJiafei Pan 43*3b0de918SJiafei Pan# Area of OCRAM reserved by ROM code 44*3b0de918SJiafei PanNXP_ROM_RSVD := 0x5900 45*3b0de918SJiafei Pan 46*3b0de918SJiafei Pan# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 47*3b0de918SJiafei Pan# Input to CST create_hdr_esbc tool 48*3b0de918SJiafei PanCSF_HDR_SZ := 0x3000 49*3b0de918SJiafei Pan 50*3b0de918SJiafei Pan# In IMAGE_BL2, compile time flag for handling Cache coherency 51*3b0de918SJiafei Pan# with CAAM for BL2 running from OCRAM 52*3b0de918SJiafei PanSEC_MEM_NON_COHERENT := yes 53*3b0de918SJiafei Pan 54*3b0de918SJiafei Pan# OCRAM MAP 55*3b0de918SJiafei PanOCRAM_START_ADDR := 0x10000000 56*3b0de918SJiafei PanOCRAM_SIZE := 0x20000 57*3b0de918SJiafei Pan 58*3b0de918SJiafei Pan# BL2 binary is placed at start of OCRAM. 59*3b0de918SJiafei Pan# Also used by create_pbl.mk. 60*3b0de918SJiafei PanBL2_BASE := 0x10000000 61*3b0de918SJiafei Pan 62*3b0de918SJiafei Pan# After BL2 bin, OCRAM is used by ROM Code: 63*3b0de918SJiafei Pan# (OCRAM_START_ADDR + BL2_BIN_SIZE) -> (NXP_ROM_RSVD - 1) 64*3b0de918SJiafei Pan 65*3b0de918SJiafei Pan# After ROM Code, OCRAM is used by CSF header. 66*3b0de918SJiafei Pan# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1) 67*3b0de918SJiafei Pan 68*3b0de918SJiafei Pan# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ) 69*3b0de918SJiafei Pan# This value should be greater than BL2_TEXT_LIMIT 70*3b0de918SJiafei Pan# Input to CST create_hdr_isbc tool 71*3b0de918SJiafei PanBL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ)))) 72*3b0de918SJiafei Pan# Covert to HEX to be used by create_pbl.mk 73*3b0de918SJiafei PanBL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc) 74*3b0de918SJiafei Pan 75*3b0de918SJiafei Pan# Core Errata 76*3b0de918SJiafei PanERRATA_A53_855873 := 1 77*3b0de918SJiafei PanERRATA_A53_1530924 := 1 78*3b0de918SJiafei Pan 79*3b0de918SJiafei Pan# SoC ERRATAS to be enabled 80*3b0de918SJiafei PanERRATA_SOC_A008850 := 1 81*3b0de918SJiafei PanERRATA_SOC_A010539 := 1 82*3b0de918SJiafei PanERRATA_SOC_A009660 := 1 83*3b0de918SJiafei Pan 84*3b0de918SJiafei Pan# DDR Errata 85*3b0de918SJiafei PanERRATA_DDR_A009663 := 1 86*3b0de918SJiafei PanERRATA_DDR_A009942 := 1 87*3b0de918SJiafei Pan 88*3b0de918SJiafei Pan# enable dynamic memory mapping 89*3b0de918SJiafei PanPLAT_XLAT_TABLES_DYNAMIC := 1 90*3b0de918SJiafei Pan 91*3b0de918SJiafei Pan# Define Endianness of each module 92*3b0de918SJiafei PanNXP_GUR_ENDIANNESS := BE 93*3b0de918SJiafei PanNXP_DDR_ENDIANNESS := BE 94*3b0de918SJiafei PanNXP_SEC_ENDIANNESS := BE 95*3b0de918SJiafei PanNXP_SFP_ENDIANNESS := BE 96*3b0de918SJiafei PanNXP_SNVS_ENDIANNESS := BE 97*3b0de918SJiafei PanNXP_ESDHC_ENDIANNESS := BE 98*3b0de918SJiafei PanNXP_QSPI_ENDIANNESS := BE 99*3b0de918SJiafei PanNXP_FSPI_ENDIANNESS := BE 100*3b0de918SJiafei PanNXP_SCFG_ENDIANNESS := BE 101*3b0de918SJiafei PanNXP_GPIO_ENDIANNESS := BE 102*3b0de918SJiafei PanNXP_IFC_ENDIANNESS := BE 103*3b0de918SJiafei Pan 104*3b0de918SJiafei PanNXP_SFP_VER := 3_2 105*3b0de918SJiafei Pan 106*3b0de918SJiafei Pan# OCRAM ECC Enabled 107*3b0de918SJiafei PanOCRAM_ECC_EN := yes 108