| #
4f6c787e |
| 09-Jun-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration
* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration
* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family
show more ...
|
| #
e577ca36 |
| 02-Feb-2024 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
docs(stm32mp2): introduce new STM32MP23 family
STM32MP23 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
docs(stm32mp2): introduce new STM32MP23 family
STM32MP23 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
H264 - 3D GPU - AI / NN - LVDS / DSI
- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
Change-Id: Iaf3dd7e0c1eda055063361af3c98855b1272d4c6
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
|
| #
07759f2b |
| 20-Apr-2023 |
Yann Gautier <yann.gautier@foss.st.com> |
docs(stm32mp2): introduce new STM32MP21 family
STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
docs(stm32mp2): introduce new STM32MP21 family
STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
CSI - LTDC
- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
Change-Id: Ie3db430bedd86c3b444bec647792be24b20a0cba
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
show more ...
|
| #
ccd580c4 |
| 16-Sep-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration
* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat
Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration
* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat(stm32mp2): add RISAB registers description
feat(stm32mp2-fdts): add BL31 info in fw-config
feat(stm32mp2): add minimal support for BL31
feat(st): manage BL31 FCONF load_info struct
show more ...
|
| #
ae84525f |
| 13-Sep-2024 |
Maxime Méré <maxime.mere@foss.st.com> |
feat(stm32mp2): manage DDR FW via FIP
This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.
DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the
feat(stm32mp2): manage DDR FW via FIP
This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.
DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the SRAM1 will be allocated to TF-A.
RISAB3 has to be configured to allow access to SRAM1.
Add image ID and update maximum number on platform side also.
Fill related descriptor information, add policy and update numbers.
DDR_TYPE variable is used to identify binary file, and image is now
added in the fiptool command line.
The DDR PHY firmware is not in TF-A repository. It can be found at
https://github.com/STMicroelectronics/stm32-ddr-phy-binary
To ease the selection of the firmware path, STM32MP_DDR_FW_PATH is added
to platform.mk file.
Change-Id: I09ab0a5c63406055a7b5ccd16d65e443de47ca2f
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
show more ...
|
| #
0dc0fda7 |
| 03-Jul-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "stm32mp2_doc_update" into integration
* changes:
feat(docs): add STM32MP2 docs links
docs(stm32mp2): correct STM32MP2 frequencies
|
| #
21b6260e |
| 29-Mar-2023 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(docs): add STM32MP2 docs links
Add links to official STMicroelectronics documentation (STM32MP2
series presentation and wiki).
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id:
feat(docs): add STM32MP2 docs links
Add links to official STMicroelectronics documentation (STM32MP2
series presentation and wiki).
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I2fca0da56bc6064c222df34493921dff3e119a22
show more ...
|
| #
7b7d23cd |
| 02-Feb-2024 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
docs(stm32mp2): correct STM32MP2 frequencies
STM32MP25xA & STM32MP25xC versions run at 1.2GHz.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I75aea682c8e3fa89e7ac1347bb7f9d02
docs(stm32mp2): correct STM32MP2 frequencies
STM32MP25xA & STM32MP25xC versions run at 1.2GHz.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I75aea682c8e3fa89e7ac1347bb7f9d02f2086222
show more ...
|
| #
cc933e1d |
| 15-Sep-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "stm32mp2" into integration
* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinc
Merge changes from topic "stm32mp2" into integration
* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files
feat(stm32mp2-fdts): introduce stm32mp25 SoCs family
feat(stm32mp2): add console configuration
feat(st): add RCC registers list
feat(st-uart): add AARCH64 stm32_console driver
feat(st): introduce new platform STM32MP2
feat(dt-bindings): add the STM32MP2 clock and reset bindings
docs(changelog): add scopes for STM32MP2
feat(docs): introduce STM32MP2 doc
refactor(docs): add a sub-menu for ST platforms
refactor(st): move plat_image_load.c
refactor(st): rename PLAT_NB_FIXED_REGS
refactor(st): move some storage definitions to common part
refactor(st): move SDMMC definitions to driver
feat(st-clock): stub fdt_get_rcc_secure_state
feat(st-clock): allow aarch64 compilation of STGEN functions
feat(st): allow AARCH64 compilation for common code
refactor(st): rename QSPI macros
show more ...
|
| #
ee5076f9 |
| 17-Mar-2023 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(docs): introduce STM32MP2 doc
STM32MP2x is a new family of microprocessors designed by
STMicroelectronics and based on Arm Cortex-A35.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Ch
feat(docs): introduce STM32MP2 doc
STM32MP2x is a new family of microprocessors designed by
STMicroelectronics and based on Arm Cortex-A35.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I741ed0a701a614817a4d0b65d3d6f4e6a79da6a9
show more ...
|