| #
79664cfc |
| 15-Dec-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I2b23e7c8,I779587af,Ic46de7a4,If753e987,I00171b05, ... into integration
* changes:
fix(layerscape): unlock write access SMMU_CBn_ACTLR
fix(nxp-ddr): add checking return value
fea
Merge changes I2b23e7c8,I779587af,Ic46de7a4,If753e987,I00171b05, ... into integration
* changes:
fix(layerscape): unlock write access SMMU_CBn_ACTLR
fix(nxp-ddr): add checking return value
feat(lx2): enable OCRAM ECC
fix(nxp-tools): fix coverity issue
fix(nxp-ddr): fix coverity issue
fix(nxp-ddr): fix underrun coverity issue
fix(nxp-drivers): fix sd secure boot failure
feat(lx2): support more variants
fix(lx2): init global data before using it
fix(ls1046a): 4 keys secureboot failure resolved
fix(nxp-crypto): fix secure boot assert inclusion
fix(nxp-crypto): fix coverity issue
fix(nxp-drivers): fix fspi coverity issue
fix(nxp-drivers): fix tzc380 memory regions config
fix(layerscape): fix nv_storage assert checking
fix(nxp-ddr): apply Max CDD values for warm boot
fix(nxp-ddr): use CDDWW for write to read delay
fix(layerscape): fix errata a008850
show more ...
|
| #
c0c157a6 |
| 07-Jun-2022 |
Kshitiz Varshney <kshitiz.varshney@nxp.com> |
fix(ls1046a): 4 keys secureboot failure resolved
Changed the size of OCRAM reserved by ROM code and increased the
size of CSF header.
Earlier, 4 keys image was exceeding boundaries and landing in
OC
fix(ls1046a): 4 keys secureboot failure resolved
Changed the size of OCRAM reserved by ROM code and increased the
size of CSF header.
Earlier, 4 keys image was exceeding boundaries and landing in
OCRAM location reserved for ROM usage.
Signed-off by:- Kshitiz Varshney <kshitiz.varshney@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I628ff7464fe0184d0553a7962d592aafd42e8137
show more ...
|
| #
1b33b58b |
| 17-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "ls1046a" into integration
* changes:
docs(layerscape): add ls1046a soc and board support
feat(ls1046aqds): add board ls1046aqds support
feat(ls1046afrwy): add ls1046a
Merge changes from topic "ls1046a" into integration
* changes:
docs(layerscape): add ls1046a soc and board support
feat(ls1046aqds): add board ls1046aqds support
feat(ls1046afrwy): add ls1046afrwy board support
feat(ls1046ardb): add ls1046ardb board support
feat(ls1046a): add new SoC platform ls1046a
fix(nxp-tools): fix tool location path for byte_swape
fix(nxp-qspi): fix include path for QSPI driver
build(changelog): add new scopes for NXP layerscape platforms
show more ...
|
| #
cc708597 |
| 20-Jan-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(ls1046a): add new SoC platform ls1046a
The LS1046A is a cost-effective, power-efficient, and highly
integrated system-on-chip (SoC) design that extends the reach
of the NXP value-performance li
feat(ls1046a): add new SoC platform ls1046a
The LS1046A is a cost-effective, power-efficient, and highly
integrated system-on-chip (SoC) design that extends the reach
of the NXP value-performance line of QorIQ communications
processors. Featuring power-efficient 64-bit Arm Cortex A72
cores with ECC-protected L1 and L2 cache memories for high
reliability, running up to 1.8 GHz.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Change-Id: I208d9bf1702410463c2b2630d31d0cd4eb7e8837
show more ...
|