1cc708597SJiafei Pan# 2cc708597SJiafei Pan# Copyright 2022 NXP 3cc708597SJiafei Pan# 4cc708597SJiafei Pan# SPDX-License-Identifier: BSD-3-Clause 5cc708597SJiafei Pan# 6cc708597SJiafei Pan# 7cc708597SJiafei Pan#------------------------------------------------------------------------------ 8cc708597SJiafei Pan# 9cc708597SJiafei Pan# This file contains the basic architecture definitions that drive the build 10cc708597SJiafei Pan# 11cc708597SJiafei Pan# ----------------------------------------------------------------------------- 12cc708597SJiafei Pan 13cc708597SJiafei PanCORE_TYPE := a72 14cc708597SJiafei Pan 15cc708597SJiafei PanCACHE_LINE := 6 16cc708597SJiafei Pan 17cc708597SJiafei Pan# set to GIC400 or GIC500 18cc708597SJiafei PanGIC := GIC400 19cc708597SJiafei Pan 20cc708597SJiafei Pan# set to CCI400 or CCN504 or CCN508 21cc708597SJiafei PanINTERCONNECT := CCI400 22cc708597SJiafei Pan 23cc708597SJiafei Pan# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 24cc708597SJiafei PanCHASSIS := 2 25cc708597SJiafei Pan 26cc708597SJiafei Pan# TZC IP Details TZC used is TZC380 or TZC400 27cc708597SJiafei PanTZC_ID := TZC400 28cc708597SJiafei Pan 29cc708597SJiafei Pan# CONSOLE Details available is NS16550 or PL011 30cc708597SJiafei PanCONSOLE := NS16550 31cc708597SJiafei Pan 32cc708597SJiafei Pan # Select the DDR PHY generation to be used 33cc708597SJiafei PanPLAT_DDR_PHY := PHY_GEN1 34cc708597SJiafei Pan 35cc708597SJiafei PanPHYS_SYS := 64 36cc708597SJiafei Pan 37cc708597SJiafei Pan# ddr controller - set to MMDC or NXP 38cc708597SJiafei PanDDRCNTLR := NXP 39cc708597SJiafei Pan 40cc708597SJiafei Pan# ddr phy - set to NXP or SNPS 41cc708597SJiafei PanDDRPHY := NXP 42cc708597SJiafei Pan 43cc708597SJiafei Pan# Area of OCRAM reserved by ROM code 44*c0c157a6SKshitiz VarshneyNXP_ROM_RSVD := 0x8000 45cc708597SJiafei Pan 46cc708597SJiafei Pan# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 47cc708597SJiafei Pan# Input to CST create_hdr_esbc tool 48*c0c157a6SKshitiz VarshneyCSF_HDR_SZ := 0x4000 49cc708597SJiafei Pan 50cc708597SJiafei Pan# In IMAGE_BL2, compile time flag for handling Cache coherency 51cc708597SJiafei Pan# with CAAM for BL2 running from OCRAM 52cc708597SJiafei PanSEC_MEM_NON_COHERENT := yes 53cc708597SJiafei Pan 54cc708597SJiafei Pan# OCRAM MAP 55cc708597SJiafei PanOCRAM_START_ADDR := 0x10000000 56cc708597SJiafei PanOCRAM_SIZE := 0x20000 57cc708597SJiafei Pan 58cc708597SJiafei Pan# BL2 binary is placed at start of OCRAM. 59cc708597SJiafei Pan# Also used by create_pbl.mk. 60cc708597SJiafei PanBL2_BASE := 0x10000000 61cc708597SJiafei Pan 62cc708597SJiafei Pan# After BL2 bin, OCRAM is used by ROM Code: 63cc708597SJiafei Pan# (OCRAM_START_ADDR + BL2_BIN_SIZE) -> (NXP_ROM_RSVD - 1) 64cc708597SJiafei Pan 65cc708597SJiafei Pan# After ROM Code, OCRAM is used by CSF header. 66cc708597SJiafei Pan# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1) 67cc708597SJiafei Pan 68cc708597SJiafei Pan# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ) 69cc708597SJiafei Pan# This value should be greater than BL2_TEXT_LIMIT 70cc708597SJiafei Pan# Input to CST create_hdr_isbc tool 71cc708597SJiafei PanBL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ)))) 72cc708597SJiafei Pan# Covert to HEX to be used by create_pbl.mk 73cc708597SJiafei PanBL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc) 74cc708597SJiafei Pan 75cc708597SJiafei Pan# Core Errata 76cc708597SJiafei PanERRATA_A72_859971 := 1 77cc708597SJiafei Pan 78cc708597SJiafei Pan# SoC ERRATAS 79cc708597SJiafei PanERRATA_SOC_A008850 := 1 80cc708597SJiafei PanERRATA_SOC_A010539 := 1 81cc708597SJiafei Pan 82cc708597SJiafei Pan# DDR Errata 83cc708597SJiafei PanERRATA_DDR_A008511 := 1 84cc708597SJiafei PanERRATA_DDR_A009803 := 1 85cc708597SJiafei PanERRATA_DDR_A009942 := 1 86cc708597SJiafei PanERRATA_DDR_A010165 := 1 87cc708597SJiafei Pan 88cc708597SJiafei Pan# enable dynamic memory mapping 89cc708597SJiafei PanPLAT_XLAT_TABLES_DYNAMIC := 1 90cc708597SJiafei Pan 91cc708597SJiafei Pan# Define Endianness of each module 92cc708597SJiafei PanNXP_GUR_ENDIANNESS := BE 93cc708597SJiafei PanNXP_DDR_ENDIANNESS := BE 94cc708597SJiafei PanNXP_SEC_ENDIANNESS := BE 95cc708597SJiafei PanNXP_SFP_ENDIANNESS := BE 96cc708597SJiafei PanNXP_SNVS_ENDIANNESS := BE 97cc708597SJiafei PanNXP_ESDHC_ENDIANNESS := BE 98cc708597SJiafei PanNXP_QSPI_ENDIANNESS := BE 99cc708597SJiafei PanNXP_FSPI_ENDIANNESS := BE 100cc708597SJiafei PanNXP_SCFG_ENDIANNESS := BE 101cc708597SJiafei PanNXP_GPIO_ENDIANNESS := BE 102cc708597SJiafei PanNXP_IFC_ENDIANNESS := BE 103cc708597SJiafei Pan 104cc708597SJiafei PanNXP_SFP_VER := 3_2 105cc708597SJiafei Pan 106cc708597SJiafei Pan# OCRAM ECC Enabled 107cc708597SJiafei PanOCRAM_ECC_EN := yes 108