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Searched refs:frequency (Results 1 – 25 of 61) sorted by relevance

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/rk3399_ARM-atf/fdts/
H A Dstm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi9 clock-frequency = <40000000>;
13 clock-frequency = <64000000>;
17 clock-frequency = <32768>;
21 clock-frequency = <32000>;
25 clock-frequency = <16000000>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi14 clock-frequency = <40000000>;
18 clock-frequency = <64000000>;
22 clock-frequency = <32768>;
26 clock-frequency = <32000>;
30 clock-frequency = <16000000>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi14 clock-frequency = <40000000>;
18 clock-frequency = <64000000>;
22 clock-frequency = <32768>;
26 clock-frequency = <32000>;
30 clock-frequency = <16000000>;
H A Dn1sdp-single-chip.dts36 clock-frequency = <60000000>;
43 clock-frequency = <23750000>;
66 clock-frequency = <400000>;
H A Da5ds.dts70 clock-frequency = <7500000>;
77 clock-frequency = <24000000>;
84 clock-frequency = <48000000>;
131 clock-frequency = <7500000>;
H A Dmorello.dtsi87 clock-frequency = <50000000>;
94 clock-frequency = <85000000>;
101 clock-frequency = <50000000>;
H A Dtc-fvp.dtsi15 clock-frequency = <LCD_TIMING_CLK>; \
29 clock-frequency = <LCD_TIMING_CLK>; \
H A Dcorstone700.dtsi53 clock-frequency = <100000000>;
61 clock-frequency = <48000000>;
69 clock-frequency = <32000000>;
H A Drtsm_ve-motherboard.dtsi16 clock-frequency = <24000000>;
23 clock-frequency = <1000000>;
30 clock-frequency = <32768>;
149 max-frequency = <12000000>;
H A Dstm32mp251.dtsi31 clock-frequency = <48000000>;
37 clock-frequency = <64000000>;
43 clock-frequency = <32768>;
49 clock-frequency = <32000>;
55 clock-frequency = <16000000>;
246 max-frequency = <166000000>;
259 max-frequency = <166000000>;
H A Dtc-base.dtsi343 clock-frequency = <1000000000>;
350 clock-frequency = <60000000>;
357 clock-frequency = <TC_UARTCLK>;
375 clock-frequency = <LCD_TIMING_CLK>;
382 clock-frequency = <LCD_TIMING_CLK>;
430 clock-frequency = <24000000>;
456 max-frequency = <25000000>;
465 clock-frequency = <1000000000>;
471 clock-frequency = <1000000000>;
H A Dcorstone700_fpga.dts33 clock-frequency = <32000000>;
H A Dcorstone700_fvp.dts39 clock-frequency = <50000000>;
H A Darm_fpga.dts70 clock-frequency = <100000000>;
77 clock-frequency = <10000000>;
H A Dstm32mp131.dtsi33 clock-frequency = <4000000>;
39 clock-frequency = <24000000>;
45 clock-frequency = <64000000>;
51 clock-frequency = <32768>;
57 clock-frequency = <32000>;
326 max-frequency = <130000000>;
339 max-frequency = <130000000>;
H A Dtc-fpga.dtsi13 clock-frequency = <LCD_TIMING_CLK>; \
H A Dstm32mp151.dtsi44 clock-frequency = <24000000>;
50 clock-frequency = <64000000>;
56 clock-frequency = <32768>;
62 clock-frequency = <32000>;
68 clock-frequency = <4000000>;
334 max-frequency = <120000000>;
348 max-frequency = <120000000>;
H A Dstm32mp157c-ev1-sp_min.dts53 spi-max-frequency = <108000000>;
/rk3399_ARM-atf/include/drivers/nxp/ddr/s32cc/
H A Dddr_init.h83 uint16_t frequency; member
116 uint16_t frequency; member
176 void set_optimal_pll(uint16_t frequency);
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_i_loadpieimage.c61 dfifrq_x10 = (10U * (uint16_t)config->uib.frequency) / 2U; in seq0bdly_program()
66 if (config->uib.frequency < 400U) { in seq0bdly_program()
68 } else if (config->uib.frequency < 533U) { in seq0bdly_program()
129 (config->uib.frequency < 333U)) { in seq0bdisableflag_program()
168 if (config->uib.frequency >= 333U) { in ppttrainsetup_program()
H A Dddrphy_phyinit_progcsrskiptrain.c53 uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2); in dfimrl_program()
115 uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
198 uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
281 uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
293 rxendly_offset_x1000000 = config->uib.frequency < 333U ?
722 memck_freq = config->uib.frequency;
H A Dddrphy_phyinit_c_initphyconfig.c149 uint32_t halffreq = config->uib.frequency / 2U; in pllctrl2_program()
191 if (config->uib.frequency >= 933U) { in ardptrinitval_program()
330 } else if (config->uib.frequency <= 933U) { in procodttimectl_program()
333 } else if (config->uib.frequency <= 1200U) { in procodttimectl_program()
573 caluclkticksper1us_x10 = (10U * config->uib.frequency) / 2U; in caluclkinfo_program()
576 if ((config->uib.frequency % 2U) != 0U) { in caluclkinfo_program()
799 if (config->uib.frequency < 333U) { in dfixlat_program()
/rk3399_ARM-atf/plat/intel/soc/common/fdts/
H A Dagilex5_fdt.dts73 clock-frequency = <100000000>;
83 clock-frequency = <7500000>;
/rk3399_ARM-atf/drivers/nxp/ddr/s32cc/
H A Dddr_init.c79 set_optimal_pll(config->frequency); in execute_training()
218 void set_optimal_pll(uint16_t frequency) in set_optimal_pll() argument
224 mmio_write_32(MASTER_PLLCTRL2, pllctrl2_value(frequency)); in set_optimal_pll()
/rk3399_ARM-atf/drivers/nxp/ddr/phy-gen2/
H A Dinput.h49 int frequency; /* memclk frequency in mhz -- round up */ member

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