Merge "fix(tc): replace vencoder with simple panel for kernel > 6.6" into integration

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")

To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.

We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d

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Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME a

Merge changes from topic "us_tc4_rebase_v2" into integration

* changes:
feat(tc): bind DPU SMMU on TC4
feat(tc): bind GPU SMMU on TC4
feat(tc): update DT for Drage GPU
feat(tc): enable SME and SME2 options for TC4
feat(tc): add new TC4 RoS definitions
feat(tc): add system generic timer register definition for TC4
feat(tc): allow TARGET_VERSION=4
feat(tc): add MHUv3 register addresses for TC4
feat(tc): add device tree binding for TC4

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feat(tc): add new TC4 RoS definitions

The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.

Change-Id: Ia62a670e47cdc98b3

feat(tc): add new TC4 RoS definitions

The TC4 uses a new RoS (Virtual Peripherals) and places them at
different address to that in TC3. Add these addresses to the DTS.

Change-Id: Ia62a670e47cdc98b3c113a670a21edc65905cafe
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc):

Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc): change GIC DT property 'interrupt-cells' to 4
feat(tc): add NI-Tower PMU node for TC3
feat(tc): setup ni-tower non-secure access for TC3

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feat(tc): change GIC DT property 'interrupt-cells' to 4

Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine

feat(tc): change GIC DT property 'interrupt-cells' to 4

Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine
to.

If an interrupt is a PPI, and the node pointed in the 4th cell must be a
subnode of the "ppi-partitions" in the GIC node. For interrupt types
other than PPI, this cell must be zero. This is a preparison for
sequential changes for interrupt partitions, as the first step, it sets
all zeros for the interrupt affinity.

Change-Id: I66490a86a27aad5db6b1a42c2d8e0d042eee46a9
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "feat(tc): support full-HD resolution for the FVP model" into integration

feat(tc): support full-HD resolution for the FVP model

Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.

Change-Id: I5e37ae79b5ceac08

feat(tc): support full-HD resolution for the FVP model

Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.

Change-Id: I5e37ae79b5ceac088a18d5acf00ff4a557bb56aa
Signed-off-by: Sergio Alves <sergio.dasilvalves@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "tc_refactor_dt_binding" into integration

* changes:
refactor(tc): move SCMI nodes into the 'firmware' node
refactor(tc): move MHUv2 property to tc2.dts
refactor(tc):

Merge changes from topic "tc_refactor_dt_binding" into integration

* changes:
refactor(tc): move SCMI nodes into the 'firmware' node
refactor(tc): move MHUv2 property to tc2.dts
refactor(tc): drop the 'mhu-protocol' property in DT binding
refactor(tc): append properties in DT bindings
refactor(tc): move SCMI clock DT binding into tc-base.dtsi
refactor(tc): introduce a new file tc-fpga.dtsi
refactor(tc): move out platform specific DT binding from tc-base.dtsi
refactor(tc): move out platform specific code from tc_vers.dtsi
refactor(tc): add platform specific DT files
refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi'
refactor(tc): introduce a new macro ADDRESSIFY()

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refactor(tc): append properties in DT bindings

This patch appends properties in DT bindings to differentiate between
FVP and FPGA. The related macros are no longer used, so they are
removed.

This p

refactor(tc): append properties in DT bindings

This patch appends properties in DT bindings to differentiate between
FVP and FPGA. The related macros are no longer used, so they are
removed.

This patch contains minor improvement for adding labels in device nodes.

Change-Id: I8d708bb7a8a9a0ed32b806abcb4e7651daadf5e6
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(tc): introduce a new file tc-fpga.dtsi

A Total Compute platform supports FVP and FPGA target. And it's possible
that these two targets have different hardware components. For this
reason, t

refactor(tc): introduce a new file tc-fpga.dtsi

A Total Compute platform supports FVP and FPGA target. And it's possible
that these two targets have different hardware components. For this
reason, this patch introduces a new file tc-fpga.dtsi for FPGA related
DT binding.

As a result, this patch moves out FVP and FPGA specific macros into
tc-fvp.dtsi and tc-fpga.dtsi respectively.

Change-Id: I48d7d30d0c500cec5500f1a2a680e8b3a276ea99
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi'

To follow up the DT naming convention, this patch renames the file
'tc_fvp.dtsi' to 'tc-fvp.dtsi'.

Change-Id: Ib74cc38eb935d3daac87fbab6de4c004b1

refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi'

To follow up the DT naming convention, this patch renames the file
'tc_fvp.dtsi' to 'tc-fvp.dtsi'.

Change-Id: Ib74cc38eb935d3daac87fbab6de4c004b1ceddcc
Signed-off-by: Leo Yan <leo.yan@arm.com>

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