1*b35ce0c4SPankaj Gupta /* 2*b35ce0c4SPankaj Gupta * Copyright 2021 NXP 3*b35ce0c4SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 4*b35ce0c4SPankaj Gupta * 5*b35ce0c4SPankaj Gupta */ 6*b35ce0c4SPankaj Gupta 7*b35ce0c4SPankaj Gupta #ifndef _INPUT_H_ 8*b35ce0c4SPankaj Gupta #define _INPUT_H_ 9*b35ce0c4SPankaj Gupta 10*b35ce0c4SPankaj Gupta enum dram_types { 11*b35ce0c4SPankaj Gupta DDR4, 12*b35ce0c4SPankaj Gupta DDR3, 13*b35ce0c4SPankaj Gupta LPDDR4, 14*b35ce0c4SPankaj Gupta LPDDR3, 15*b35ce0c4SPankaj Gupta LPDDR2, 16*b35ce0c4SPankaj Gupta DDR5, 17*b35ce0c4SPankaj Gupta }; 18*b35ce0c4SPankaj Gupta 19*b35ce0c4SPankaj Gupta enum dimm_types { 20*b35ce0c4SPankaj Gupta UDIMM, 21*b35ce0c4SPankaj Gupta SODIMM, 22*b35ce0c4SPankaj Gupta RDIMM, 23*b35ce0c4SPankaj Gupta LRDIMM, 24*b35ce0c4SPankaj Gupta NODIMM, 25*b35ce0c4SPankaj Gupta }; 26*b35ce0c4SPankaj Gupta 27*b35ce0c4SPankaj Gupta struct input_basic { 28*b35ce0c4SPankaj Gupta enum dram_types dram_type; 29*b35ce0c4SPankaj Gupta enum dimm_types dimm_type; 30*b35ce0c4SPankaj Gupta int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4 31*b35ce0c4SPankaj Gupta */ 32*b35ce0c4SPankaj Gupta /* not used for protocols other than lpddr4 */ 33*b35ce0c4SPankaj Gupta int num_dbyte; /* number of dbytes physically instantiated */ 34*b35ce0c4SPankaj Gupta int num_active_dbyte_dfi0; /* number of active dbytes to be 35*b35ce0c4SPankaj Gupta * controlled by dfi0 36*b35ce0c4SPankaj Gupta */ 37*b35ce0c4SPankaj Gupta int num_active_dbyte_dfi1; /* number of active dbytes to be 38*b35ce0c4SPankaj Gupta * controlled by dfi1. Not used for 39*b35ce0c4SPankaj Gupta * protocols other than lpddr3 and 40*b35ce0c4SPankaj Gupta * lpddr4 41*b35ce0c4SPankaj Gupta */ 42*b35ce0c4SPankaj Gupta int num_anib; /* number of anibs physically instantiated */ 43*b35ce0c4SPankaj Gupta int num_rank_dfi0; /* number of ranks in dfi0 channel */ 44*b35ce0c4SPankaj Gupta int num_rank_dfi1; /* number of ranks in dfi1 channel */ 45*b35ce0c4SPankaj Gupta int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram 46*b35ce0c4SPankaj Gupta * type 47*b35ce0c4SPankaj Gupta */ 48*b35ce0c4SPankaj Gupta int num_pstates; 49*b35ce0c4SPankaj Gupta int frequency; /* memclk frequency in mhz -- round up */ 50*b35ce0c4SPankaj Gupta int pll_bypass; /* pll bypass enable */ 51*b35ce0c4SPankaj Gupta int dfi_freq_ratio; /* selected dfi frequency ratio */ 52*b35ce0c4SPankaj Gupta int dfi1exists; /* whether they phy config has dfi1 channel */ 53*b35ce0c4SPankaj Gupta int train2d; 54*b35ce0c4SPankaj Gupta int hard_macro_ver; 55*b35ce0c4SPankaj Gupta int read_dbienable; 56*b35ce0c4SPankaj Gupta int dfi_mode; /* no longer used */ 57*b35ce0c4SPankaj Gupta }; 58*b35ce0c4SPankaj Gupta 59*b35ce0c4SPankaj Gupta struct input_advanced { 60*b35ce0c4SPankaj Gupta int d4rx_preamble_length; 61*b35ce0c4SPankaj Gupta int d4tx_preamble_length; 62*b35ce0c4SPankaj Gupta int ext_cal_res_val; /* external pull-down resistor */ 63*b35ce0c4SPankaj Gupta int is2ttiming; 64*b35ce0c4SPankaj Gupta int odtimpedance; 65*b35ce0c4SPankaj Gupta int tx_impedance; 66*b35ce0c4SPankaj Gupta int atx_impedance; 67*b35ce0c4SPankaj Gupta int mem_alert_en; 68*b35ce0c4SPankaj Gupta int mem_alert_puimp; 69*b35ce0c4SPankaj Gupta int mem_alert_vref_level; 70*b35ce0c4SPankaj Gupta int mem_alert_sync_bypass; 71*b35ce0c4SPankaj Gupta int dis_dyn_adr_tri; 72*b35ce0c4SPankaj Gupta int phy_mstr_train_interval; 73*b35ce0c4SPankaj Gupta int phy_mstr_max_req_to_ack; 74*b35ce0c4SPankaj Gupta int wdqsext; 75*b35ce0c4SPankaj Gupta int cal_interval; 76*b35ce0c4SPankaj Gupta int cal_once; 77*b35ce0c4SPankaj Gupta int dram_byte_swap; 78*b35ce0c4SPankaj Gupta int rx_en_back_off; 79*b35ce0c4SPankaj Gupta int train_sequence_ctrl; 80*b35ce0c4SPankaj Gupta int phy_gen2_umctl_opt; 81*b35ce0c4SPankaj Gupta int phy_gen2_umctl_f0rc5x; 82*b35ce0c4SPankaj Gupta int tx_slew_rise_dq; 83*b35ce0c4SPankaj Gupta int tx_slew_fall_dq; 84*b35ce0c4SPankaj Gupta int tx_slew_rise_ac; 85*b35ce0c4SPankaj Gupta int tx_slew_fall_ac; 86*b35ce0c4SPankaj Gupta int enable_high_clk_skew_fix; 87*b35ce0c4SPankaj Gupta int disable_unused_addr_lns; 88*b35ce0c4SPankaj Gupta int phy_init_sequence_num; 89*b35ce0c4SPankaj Gupta int cs_mode; /* rdimm */ 90*b35ce0c4SPankaj Gupta int cast_cs_to_cid; /* rdimm */ 91*b35ce0c4SPankaj Gupta }; 92*b35ce0c4SPankaj Gupta 93*b35ce0c4SPankaj Gupta struct input { 94*b35ce0c4SPankaj Gupta struct input_basic basic; 95*b35ce0c4SPankaj Gupta struct input_advanced adv; 96*b35ce0c4SPankaj Gupta unsigned int mr[7]; 97*b35ce0c4SPankaj Gupta unsigned int cs_d0; 98*b35ce0c4SPankaj Gupta unsigned int cs_d1; 99*b35ce0c4SPankaj Gupta unsigned int mirror; 100*b35ce0c4SPankaj Gupta unsigned int odt[4]; 101*b35ce0c4SPankaj Gupta unsigned int rcw[16]; 102*b35ce0c4SPankaj Gupta unsigned int rcw3x; 103*b35ce0c4SPankaj Gupta unsigned int vref; 104*b35ce0c4SPankaj Gupta }; 105*b35ce0c4SPankaj Gupta 106*b35ce0c4SPankaj Gupta #endif 107