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Searched refs:clock (Results 1 – 25 of 108) sorted by relevance

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/rk3399_ARM-atf/plat/rockchip/common/scmi/
H A Dscmi_clock.c34 rk_scmi_clock_t *clock; in plat_scmi_clock_get_name() local
36 clock = rockchip_scmi_get_clock(agent_id, scmi_id); in plat_scmi_clock_get_name()
37 if (clock == NULL) in plat_scmi_clock_get_name()
40 return clock->name; in plat_scmi_clock_get_name()
51 rk_scmi_clock_t *clock; in plat_scmi_clock_rates_array() local
53 clock = rockchip_scmi_get_clock(agent_id, scmi_id); in plat_scmi_clock_rates_array()
54 if (clock == NULL) in plat_scmi_clock_rates_array()
57 rate_table = clock->rate_table; in plat_scmi_clock_rates_array()
62 *nb_elts = clock->rate_cnt; in plat_scmi_clock_rates_array()
66 if (start_idx + *nb_elts > clock->rate_cnt) in plat_scmi_clock_rates_array()
[all …]
H A Drockchip_common_clock.c39 static unsigned long clk_scmi_common_get_parent_rate(rk_scmi_clock_t *clock, in clk_scmi_common_get_parent_rate() argument
44 if (clock->is_dynamic_prate != 0) { in clk_scmi_common_get_parent_rate()
45 p_clock = rockchip_scmi_get_clock(0, clock->parent_table[id]); in clk_scmi_common_get_parent_rate()
53 return clock->parent_table[id]; in clk_scmi_common_get_parent_rate()
57 unsigned long clk_scmi_common_get_rate(rk_scmi_clock_t *clock) in clk_scmi_common_get_rate() argument
61 sel = mmio_read_32(clock->info[MUX_ADDR_INFO]) >> in clk_scmi_common_get_rate()
62 clock->info[MUX_SHIFT_INFO]; in clk_scmi_common_get_rate()
63 sel = sel & (BIT(clock->info[MUX_WIDTH_INFO]) - 1); in clk_scmi_common_get_rate()
64 div = mmio_read_32(clock->info[DIV_ADDR_INFO]) >> in clk_scmi_common_get_rate()
65 clock->info[DIV_SHIFT_INFO]; in clk_scmi_common_get_rate()
[all …]
H A Dscmi_clock.h17 unsigned long (*get_rate)(struct rk_scmi_clock *clock);
18 int (*set_rate)(struct rk_scmi_clock *clock, unsigned long rate);
19 int (*set_status)(struct rk_scmi_clock *clock, bool status);
53 unsigned long clk_scmi_common_get_rate(rk_scmi_clock_t *clock);
54 int clk_scmi_common_set_rate(rk_scmi_clock_t *clock, unsigned long rate);
55 int clk_scmi_common_set_status(rk_scmi_clock_t *clock, bool status);
/rk3399_ARM-atf/plat/intel/soc/n5x/soc/
H A Dn5x_clock_manager.c25 uint64_t clock = 0; in clk_get_pll_output_hz() local
33 clock = mmio_read_32(scr_reg); in clk_get_pll_output_hz()
37 clock = CLKMGR_INTOSC_HZ; in clk_get_pll_output_hz()
42 clock = mmio_read_32(scr_reg); in clk_get_pll_output_hz()
58 return ((clock * 2 * (divf + 1)) / ((divr + 1) * power)); in clk_get_pll_output_hz()
63 uint32_t clock = 0; in get_l4_clk() local
79 clock = clk_get_pll_output_hz(); in get_l4_clk()
80 clock /= 1 + mainpll_c1cnt; in get_l4_clk()
84 clock = clk_get_pll_output_hz(); in get_l4_clk()
85 clock /= 1 + perpll_c1cnt; in get_l4_clk()
[all …]
/rk3399_ARM-atf/fdts/
H A Drtsm_ve-motherboard.dtsi14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24000000>;
17 clock-output-names = "v2m:clk24mhz";
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <1000000>;
24 clock-output-names = "v2m:refclk1mhz";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
[all …]
H A Dcorstone700.dtsi51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <100000000>;
54 clock-output-names = "apb_pclk";
58 /* Reference 24MHz clock x 2 */
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <48000000>;
62 clock-output-names = "smclk";
66 /* UART clock - 32MHz */
[all …]
H A Dmorello.dtsi62 clock-names = "apb_pclk";
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <50000000>;
88 clock-output-names = "apb_pclk";
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <85000000>;
95 clock-output-names = "iofpga:aclk";
99 compatible = "fixed-clock";
[all …]
H A Da5ds.dts68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <7500000>;
71 clock-output-names = "apb_pclk";
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <24000000>;
78 clock-output-names = "apb_pclk";
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
[all …]
H A Dfvp-ve-Cortex-A5x1.dts56 clock-names = "pxlclk";
81 /* CPU and internal AXI reference clock */
85 #clock-cells = <0>;
86 clock-output-names = "oscclk0";
90 /* Multiplexed AXI master clock */
94 #clock-cells = <0>;
95 clock-output-names = "oscclk1";
103 #clock-cells = <0>;
104 clock-output-names = "oscclk2";
112 #clock-cells = <0>;
[all …]
H A Dn1sdp-single-chip.dts34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <60000000>;
37 clock-output-names = "iofpga_clk";
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <23750000>;
44 clock-output-names = "hdlcdclk";
52 clock-names = "pxlclk";
66 clock-frequency = <400000>;
H A Dtc-base.dtsi37 clock-names = "aclk"
41 clock-names = "pxclk"
45 clock-names = "pxclk" \
50 clock-names = "aclk"
54 clock-names = "pxclk", "aclk"
267 clock-names = "apb_pclk";
277 clock-names = "apb_pclk";
298 #clock-cells = <1>;
303 #clock-cells = <1>;
341 compatible = "fixed-clock";
[all …]
H A Dmorello-coresight.dtsi20 clock-names = "apb_pclk";
28 clock-names = "apb_pclk";
43 clock-names = "apb_pclk";
51 clock-names = "apb_pclk";
66 clock-names = "apb_pclk";
74 clock-names = "apb_pclk";
89 clock-names = "apb_pclk";
97 clock-names = "apb_pclk";
165 clock-names = "apb_pclk";
179 clock-names = "apb_pclk";
[all …]
H A Darm_fpga.dts68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <100000000>;
71 clock-output-names = "apb_pclk";
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <10000000>;
78 clock-output-names = "uartclk";
86 clock-names = "uartclk", "apb_pclk";
H A Dstm32mp257d-ultra-fly-sbc-ca35tdcid-rcc.dtsi9 clock-frequency = <40000000>;
13 clock-frequency = <64000000>;
17 clock-frequency = <32768>;
21 clock-frequency = <32000>;
25 clock-frequency = <16000000>;
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi14 clock-frequency = <40000000>;
18 clock-frequency = <64000000>;
22 clock-frequency = <32768>;
26 clock-frequency = <32000>;
30 clock-frequency = <16000000>;
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi14 clock-frequency = <40000000>;
18 clock-frequency = <64000000>;
22 clock-frequency = <32768>;
26 clock-frequency = <32000>;
30 clock-frequency = <16000000>;
H A Dtc-fvp.dtsi15 clock-frequency = <LCD_TIMING_CLK>; \
29 clock-frequency = <LCD_TIMING_CLK>; \
59 clock-names = "apb_pclk";
67 clock-names = "KMIREFCLK", "apb_pclk";
75 clock-names = "KMIREFCLK", "apb_pclk";
H A Dmorello-soc.dts231 clock-names = "aclk";
238 clock-names = "pxclk";
258 clock-frequency = <100000>;
278 /* 77.1 MHz derived from 24 MHz reference clock */
279 compatible = "fixed-clock";
280 #clock-cells = <0>;
281 clock-frequency = <350000000>;
282 clock-output-names = "aclk";
297 clock-names = "clk_mali";
302 compatible = "fixed-clock";
[all …]
H A Dstm32mp131.dtsi6 #include <dt-bindings/clock/stm32mp13-clks.h>
23 clock-names = "cpu";
31 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-frequency = <4000000>;
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <24000000>;
43 #clock-cells = <0>;
44 compatible = "fixed-clock";
[all …]
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_scmi.c131 struct stm32_scmi_clk *clock; member
139 .clock = stm32_scmi0_clock,
145 .clock = stm32_scmi1_clock,
230 return &resource->clock[n]; in find_clock()
252 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); in plat_scmi_clock_get_name() local
254 if ((clock == NULL) || in plat_scmi_clock_get_name()
255 !stm32mp_nsec_can_access_clock(clock->clock_id)) { in plat_scmi_clock_get_name()
259 return clock->name; in plat_scmi_clock_get_name()
266 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); in plat_scmi_clock_rates_array() local
268 if (clock == NULL) { in plat_scmi_clock_rates_array()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c287 static int clk_scmi_dsu_set_rate(rk_scmi_clock_t *clock, unsigned long rate);
362 static int clk_scmi_cpul_set_rate(rk_scmi_clock_t *clock, unsigned long rate) in clk_scmi_cpul_set_rate() argument
372 ret = clk_scmi_dsu_set_rate(clock, rate); in clk_scmi_cpul_set_rate()
419 static unsigned long clk_scmi_cpul_get_rate(rk_scmi_clock_t *clock) in clk_scmi_cpul_get_rate() argument
448 static int clk_scmi_cpul_set_status(rk_scmi_clock_t *clock, bool status) in clk_scmi_cpul_set_status() argument
534 static int clk_scmi_cpub01_set_rate(rk_scmi_clock_t *clock, unsigned long rate) in clk_scmi_cpub01_set_rate() argument
589 static unsigned long clk_scmi_cpub01_get_rate(rk_scmi_clock_t *clock) in clk_scmi_cpub01_get_rate() argument
617 static int clk_scmi_cpub01_set_status(rk_scmi_clock_t *clock, bool status) in clk_scmi_cpub01_set_status() argument
703 static int clk_scmi_cpub23_set_rate(rk_scmi_clock_t *clock, unsigned long rate) in clk_scmi_cpub23_set_rate() argument
758 static unsigned long clk_scmi_cpub23_get_rate(rk_scmi_clock_t *clock) in clk_scmi_cpub23_get_rate() argument
[all …]
/rk3399_ARM-atf/plat/amd/versal2/
H A Dscmi.c211 struct scmi_clk *clock; member
221 .clock = scmi0_clock,
246 ret = &resource->clock[n]; in clk_find()
272 const struct scmi_clk *clock = clk_find(agent_id, scmi_id); in plat_scmi_clock_get_name() local
275 if (clock == NULL) { in plat_scmi_clock_get_name()
278 VERBOSE("SCMI: CLK: id: %d, get_name: %s\n", scmi_id, clock->name); in plat_scmi_clock_get_name()
280 ret = clock->name; in plat_scmi_clock_get_name()
290 const struct scmi_clk *clock = clk_find(agent_id, scmi_id); in plat_scmi_clock_rates_array() local
293 if (clock == NULL) { in plat_scmi_clock_rates_array()
306 *array = clock->rate; in plat_scmi_clock_rates_array()
[all …]
/rk3399_ARM-atf/drivers/st/crypto/
H A Dstm32_rng.c70 unsigned long clock; member
103 clock_rate = clk_get_rate(stm32_rng.clock); in stm32_rng_clock_freq_restrain()
114 VERBOSE("RNG clk rate : %lu\n", clk_get_rate(stm32_rng.clock) >> clock_div); in stm32_rng_clock_freq_restrain()
258 if ((stm32_rng.base == 0U) || (stm32_rng.clock == 0U)) { in stm32_rng_select()
277 if (stm32_rng.clock != 0U) { in stm32_rng_init()
309 if (dt_rng.clock < 0) { in stm32_rng_init()
313 stm32_rng.clock = (unsigned long)dt_rng.clock; in stm32_rng_init()
314 clk_enable(stm32_rng.clock); in stm32_rng_init()
318 rng.clock = stm32_rng.clock; in stm32_rng_init()
348 if ((rng.clock != 0U) && (rng.base != 0U)) { in stm32_rng_init()
H A Dstm32_hash.c78 unsigned int clock; member
217 ret = clk_enable(stm32_hash.clock); in stm32_hash_update()
261 clk_disable(stm32_hash.clock); in stm32_hash_update()
270 ret = clk_enable(stm32_hash.clock); in stm32_hash_final()
278 clk_disable(stm32_hash.clock); in stm32_hash_final()
293 clk_disable(stm32_hash.clock); in stm32_hash_final()
313 if (clk_enable(stm32_hash.clock) != 0) { in stm32_hash_init()
320 clk_disable(stm32_hash.clock); in stm32_hash_init()
343 if (hash_info.clock < 0) { in stm32_hash_register()
348 stm32_hash.clock = hash_info.clock; in stm32_hash_register()
[all …]
/rk3399_ARM-atf/drivers/st/iwdg/
H A Dstm32_iwdg.c34 unsigned long clock; member
64 clk_enable(iwdg->clock); in stm32_iwdg_refresh()
69 clk_disable(iwdg->clock); in stm32_iwdg_refresh()
97 iwdg->clock = (unsigned long)dt_info.clock; in stm32_iwdg_init()

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