Merge "fix(versal2): remove extraneous parentheses" into integration

fix(versal2): remove extraneous parentheses

While compiling TF-A with Armclang, the following error was observed.
To fix it, the extraneous parentheses around the comparison were
removed to silence

fix(versal2): remove extraneous parentheses

While compiling TF-A with Armclang, the following error was observed.
To fix it, the extraneous parentheses around the comparison were
removed to silence the warning.

plat/amd/versal2/scmi.c:322:13: error: equality comparison with
extraneous parentheses [-Werror,-Wparentheses-equality]
if ((clock == NULL)) {

Change-Id: I51f955dd15d5020598c9e4ff2f7f92b55a909f9b
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(v

Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(versal): modify function to have single return
fix(xilinx): modify function to have single return
fix(zynqmp): modify function to have single return
fix(versal-net): add unsigned suffix to match data type
fix(versal): add unsigned suffix to match data type
fix(versal2): add missing curly braces
fix(versal-net): add missing curly braces
fix(zynqmp): add missing curly braces

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fix(versal2): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store t

fix(versal2): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.

Change-Id: Ib152831e84f5ead5b57fd713ebfedb1f3340a727
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement bod

fix(versal2): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I546cf47edc6332ee193b4771c88ae30553687f19
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_fix_plat_data_types" into integration

* changes:
fix(versal2): typecast operands to match data type
fix(versal): typecast operands to match data type
fix(versal-

Merge changes from topic "xlnx_fix_plat_data_types" into integration

* changes:
fix(versal2): typecast operands to match data type
fix(versal): typecast operands to match data type
fix(versal-net): typecast operands to match data type
fix(xilinx): typecast operands to match data type
fix(zynqmp): typecast operands to match data type
fix(versal-net): typecast operands to match data type
fix(versal): typecast operands to match data type
fix(xilinx): typecast operands to match data type
fix(zynqmp): typecast operands to match data type
fix(versal2): typecast expressions to match data type
fix(versal-net): typecast expressions to match data type
fix(versal): typecast expressions to match data type
fix(xilinx): typecast expressions to match data type
fix(zynqmp): typecast expressions to match data type
fix(zynqmp): align essential type categories
fix(zynqmp): typecast expression to match data type
fix(xilinx): typecast expression to match data type

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fix(versal2): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a

fix(versal2): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I37ec9f8d716347df9acea5eb084f5a423a32a058
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): typecast expressions to match data type

This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have th

fix(versal2): typecast expressions to match data type

This corrects the MISRA violation C2012-10.4:
Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Ia352e3cf261b52777c1c431701e1e6c3be9cd279
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_fix_plat_const_preced" into integration

* changes:
fix(versal2): explicitly check operators precedence
fix(versal-net): explicitly check operators precedence
fix

Merge changes from topic "xlnx_fix_plat_const_preced" into integration

* changes:
fix(versal2): explicitly check operators precedence
fix(versal-net): explicitly check operators precedence
fix(versal): explicitly check operators precedence
fix(xilinx): explicitly check operators precedence
fix(zynqmp): explicitly check operators precedence
fix(versal2): add const qualifier
fix(versal): add const qualifier
fix(zynqmp): add const qualifier

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fix(versal2): explicitly check operators precedence

This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression i

fix(versal2): explicitly check operators precedence

This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression in parentheses to maintain
the precedence.

Change-Id: I33028cf220fa0768f8f266db294c42810f62b61c
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): add const qualifier

This correct the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer variables and func

fix(versal2): add const qualifier

This correct the MISRA violation C2012-8.13:
A pointer should point to a const-qualified type whenever possible.
Added const qualifier to pointer variables and function arguments.

Change-Id: I3c1dfa4e5be438df4483a2b5937ee2e7c75e25ab
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge "fix(versal2): correct the UFS clock rates" into integration

fix(versal2): correct the UFS clock rates

Update the UFS clock rates as per the expected range
- Update the clock rates of "ufs_phy_clk" and "ufs_ref_pclk" to 26MHz
as 100MHz is not the valid clock

fix(versal2): correct the UFS clock rates

Update the UFS clock rates as per the expected range
- Update the clock rates of "ufs_phy_clk" and "ufs_ref_pclk" to 26MHz
as 100MHz is not the valid clock rate for these two clocks.
- cpu_clock rate (908KHz) is not valid clock for UFS, hence skip setting
up UFS clocks to cpu_clock for SPP platform.

Change-Id: I31863619ca1bd527df283d1636493dd8fce18809
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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Merge "feat(versal2): add dummy implementation for SCMI PD" into integration

Merge "fix(versal2): add ufs specific features support" into integration

fix(versal2): add ufs specific features support

Following IOCTL IDs are required for UFS specific functionalities.

IOCTL ID - 40(IOCTL_UFS_TXRX_CFGRDY_GET)
This gives the Tx_Rx_config_rdy_signal_mo

fix(versal2): add ufs specific features support

Following IOCTL IDs are required for UFS specific functionalities.

IOCTL ID - 40(IOCTL_UFS_TXRX_CFGRDY_GET)
This gives the Tx_Rx_config_rdy_signal_mon(0xF1061054) register value
which contains the Tx and Rx lanes configuration ready signal information.

IOCTL ID - 41(IOCTL_UFS_SRAM_CSR_SEL)
Select - 0(IOCTL_UFS_SRAM_CSR_SET)
This will allow to set sram control and status register (0xF106104C)
with the value provided by driver.

Select - 1(IOCTL_UFS_SRAM_CSR_GET)
This should return the sram control and status register (0xF106104C) value
to the driver.

UFS Host reset assert/de-assert(using SCMI) support is added.
register address : 0xF1260340

UFS PHY reset assert/de-assert(using SCMI) support is added.
register address : 0xF1061050

Change-Id: I5368cc7251350946bd5ddb3a4c817b75e1d4a43e
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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feat(versal2): add dummy implementation for SCMI PD

Add dummy implementation of power domain. There is dwc3 usb driver which
requires power domain to be setup and make sense to have interface prepar

feat(versal2): add dummy implementation for SCMI PD

Add dummy implementation of power domain. There is dwc3 usb driver which
requires power domain to be setup and make sense to have interface prepared
even it is not doing anything. When this runs on real HW functionality will
be extended.

Change-Id: I68151edc3ab817da3308e7c21af57a3355a17d37
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "feat(versal2): add support for AMD Versal Gen 2 platform" into integration

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>

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