| #
9526ad60 |
| 02-Jun-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st_fixes" into integration
* changes:
fix(st-iwdg): remove num_irq
fix(st-drivers): remove useless field in fixed regul
fix(st-bsec): remove useless defines in BSEC3
Merge changes from topic "st_fixes" into integration
* changes:
fix(st-iwdg): remove num_irq
fix(st-drivers): remove useless field in fixed regul
fix(st-bsec): remove useless defines in BSEC3
fix(st-bsec): rename OTPSR field
fix(st-crypto): do not set IPRST if BUSY flag is present
fix(st-ddr): bad refresh update level toggle sequence
fix(st-ddr): remove TODO in STM32MP2 driver
fix(stm32mp2): correct typo in definition header
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|
| #
9adc4270 |
| 19-Dec-2024 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
fix(st-iwdg): remove num_irq
Remove the unused field num_irq in stm32_iwdg_instance struct.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa7ae53d41ac654173b78226e3ed11
fix(st-iwdg): remove num_irq
Remove the unused field num_irq in stm32_iwdg_instance struct.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa7ae53d41ac654173b78226e3ed11d812430fa4
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|
| #
0ca4b4b7 |
| 22-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "clock_framework" into integration
* changes:
feat(st): use newly introduced clock framework
feat(clk): add a minimal clock framework
|
| #
33667d29 |
| 30-Aug-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().
Change-Id:
feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().
Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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|
| #
aa8390c2 |
| 16-Jul-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "drivers/stm32_iwdg: register IWDG resources as secure or not" into integration
|
| #
bcc360f7 |
| 02-Dec-2019 |
Etienne Carriere <etienne.carriere@st.com> |
drivers/stm32_iwdg: register IWDG resources as secure or not
Register in the shared resources driver the secure or non-secure state
of the IWDG instances.
Change-Id: I3a3bc9525447f6a2a465891ca3a3fd
drivers/stm32_iwdg: register IWDG resources as secure or not
Register in the shared resources driver the secure or non-secure state
of the IWDG instances.
Change-Id: I3a3bc9525447f6a2a465891ca3a3fd5fe664ca07
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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| #
0289ab9e |
| 10-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "yg/stm32mp1_wdg_updates" into integration
* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1:
Merge changes from topic "yg/stm32mp1_wdg_updates" into integration
* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1: move check_header() to common code
stm32mp1: keep console during runtime
stm32mp1: sp_min: initialize MMU and cache earlier
stm32mp1: add support for LpDDR3
stm32mp1: use a common function to check spinlock is available
clk: stm32mp: enable RTCAPB clock for dual-core chips
stm32mp1: check if the SoC is single core
stm32mp1: print information about board
stm32mp1: print information about SoC
stm32mp1: add watchdog support
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| #
73680c23 |
| 04-Jun-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is
stm32mp1: add watchdog support
Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is not started by default. It can be started after an HW
reset if the dedicated OTP is fused.
The watchdog also needs to be frozen if a debugger is attached.
This is done by configuring the correct bits in DBGMCU.
This configuration is allowed by checking BSEC properties.
An increase of BL2 size is also required when adding this new code.
Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
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