| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_clock_manager.c | 608 uint32_t clk_rate; in clkmgr_get_rate() local
612 clk_rate = get_mpu_clk(); in clkmgr_get_rate()
616 clk_rate = get_l4_main_clk(); in clkmgr_get_rate()
620 clk_rate = get_l4_mp_clk(); in clkmgr_get_rate()
624 clk_rate = get_l4_sp_clk(); in clkmgr_get_rate()
628 clk_rate = get_emaca_clk(); in clkmgr_get_rate()
632 clk_rate = get_sdmmc_clk(); in clkmgr_get_rate()
636 clk_rate = get_uart_clk(); in clkmgr_get_rate()
640 clk_rate = get_wdt_clk(); in clkmgr_get_rate()
645 clk_rate = 0; in clkmgr_get_rate()
[all …]
|
| /rk3399_ARM-atf/plat/st/common/ |
| H A D | stm32mp_common.c | 238 static void set_console(uintptr_t base, uint32_t clk_rate) in set_console() argument
242 if (console_stm32_register(base, clk_rate, in set_console()
259 uint32_t clk_rate = 0U; in stm32mp_uart_console_setup() local
296 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock); in stm32mp_uart_console_setup()
299 set_console(dt_uart_info.base, clk_rate); in stm32mp_uart_console_setup()
|
| /rk3399_ARM-atf/include/drivers/synopsys/ |
| H A D | dw_mmc.h | 16 int clk_rate; member
|
| /rk3399_ARM-atf/include/drivers/st/ |
| H A D | stm32_sdmmc2.h | 17 unsigned int clk_rate; member
|
| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | socfpga_private.h | 17 .clk_rate = (clk), \
|
| /rk3399_ARM-atf/drivers/st/mmc/ |
| H A D | stm32_sdmmc2.c | 207 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); in stm32_sdmmc2_init()
486 uint32_t clk_rate = sdmmc2_params.clk_rate; in stm32_sdmmc2_set_ios() local
523 clock_div = div_round_up(clk_rate, freq * 2U); in stm32_sdmmc2_set_ios()
802 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); in stm32_sdmmc2_mmc_init()
805 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, in stm32_sdmmc2_mmc_init()
|
| /rk3399_ARM-atf/plat/hisilicon/poplar/include/ |
| H A D | hi3798cv200.h | 75 .clk_rate = 25 * 1000 * 1000, \
|
| /rk3399_ARM-atf/include/drivers/rpi3/sdhost/ |
| H A D | rpi3_sdhost.h | 17 uint32_t clk_rate; member
|
| /rk3399_ARM-atf/plat/imx/imx8m/imx8mm/ |
| H A D | imx8mm_bl2_el3_setup.c | 58 params.clk_rate = 50000000; in imx8mm_usdhc_setup()
|
| /rk3399_ARM-atf/plat/imx/imx7/warp7/ |
| H A D | warp7_bl2_el3_setup.c | 107 params.clk_rate = 25000000; in warp7_usdhc_setup()
|
| /rk3399_ARM-atf/drivers/synopsys/emmc/ |
| H A D | dw_mmc.c | 165 if ((dw_params.clk_rate / (2 * div)) <= clk) { in dw_set_clk()
423 (params->clk_rate > 0) && in dw_mmc_init()
430 mmc_init(&dw_mmc_ops, params->clk_rate, params->bus_width, in dw_mmc_init()
|
| /rk3399_ARM-atf/drivers/rpi3/sdhost/ |
| H A D | rpi3_sdhost.c | 239 rpi3_sdhost_params.clk_rate = 0; in rpi3_sdhost_reset()
415 rpi3_sdhost_params.clk_rate = max_clk / (div + 2); in rpi3_sdhost_set_clock()
417 rpi3_sdhost_params.clk_rate) in rpi3_sdhost_set_clock()
625 mmc_init(&rpi3_sdhost_ops, params->clk_rate, params->bus_width, in rpi3_sdhost_init()
|
| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_bl1_setup.c | 101 params.clk_rate = 24 * 1000 * 1000; in bl1_platform_setup()
|
| H A D | hikey_bl2_setup.c | 322 params.clk_rate = 24 * 1000 * 1000; in bl2_platform_setup()
|
| /rk3399_ARM-atf/plat/imx/imx7/picopi/ |
| H A D | picopi_bl2_el3_setup.c | 101 params.clk_rate = 25000000; in picopi_usdhc_setup()
|
| /rk3399_ARM-atf/plat/rpi/rpi3/ |
| H A D | rpi3_bl2_setup.c | 44 params.clk_rate = 50000000; in rpi3_sdhost_setup()
|
| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/ |
| H A D | plat_bl2_el3_setup.c | 87 params.clk_rate = 25000000; in init_s32g_usdhc()
|
| /rk3399_ARM-atf/drivers/imx/usdhc/ |
| H A D | imx_usdhc.h | 15 unsigned int clk_rate; member
|
| H A D | imx_usdhc.c | 458 mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width, in imx_usdhc_init()
|
| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/ |
| H A D | apusys_power.c | 29 static void get_pll_pcw(uint32_t clk_rate, uint32_t *r1, uint32_t *r2) in get_pll_pcw() argument
31 unsigned int fvco = clk_rate; in get_pll_pcw()
|
| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/ |
| H A D | apusys_power.c | 239 static void get_pll_pcw(const uint32_t clk_rate, uint32_t *r1, uint32_t *r2) in get_pll_pcw() argument
241 unsigned int fvco = clk_rate; in get_pll_pcw()
|
| /rk3399_ARM-atf/include/drivers/cadence/ |
| H A D | cdns_sdmmc.h | 546 int clk_rate; member
|
| /rk3399_ARM-atf/drivers/cadence/emmc/ |
| H A D | cdns_sdmmc.c | 730 (params->clk_rate > 0) && in cdns_mmc_init()
747 result = mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width, in cdns_mmc_init()
|
| /rk3399_ARM-atf/docs/ |
| H A D | change-log.md | 1227 …- fix clk_rate and bus_width type ([3d16507](https://review.trustedfirmware.org/plugins/gitiles/TF…
|