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/rk3399_ARM-atf/plat/imx/common/include/
H A Dimx_clock.h27 #define CCM_CCGR_SETTING0_DOM_CLK_RUN BIT(0)
28 #define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT BIT(1)
29 #define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS (BIT(1) | BIT(0))
31 #define CCM_CCGR_SETTING1_DOM_CLK_RUN BIT(4)
32 #define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT BIT(5)
33 #define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS (BIT(5) | BIT(4))
35 #define CCM_CCGR_SETTING2_DOM_CLK_RUN BIT(8)
36 #define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT BIT(9)
37 #define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS (BIT(9) | BIT(8))
39 #define CCM_CCGR_SETTING3_DOM_CLK_RUN BIT(12)
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/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_reg.h546 #define BCLK_CG_EN_LSB BIT(0) /* 1b */
547 #define PROJECT_CODE_LSB BIT(16) /* 16b */
549 #define POWER_ON_VAL0_LSB BIT(0) /* 32b */
551 #define POWER_ON_VAL1_LSB BIT(0) /* 32b */
553 #define POWER_ON_VAL2_LSB BIT(0) /* 32b */
555 #define POWER_ON_VAL3_LSB BIT(0) /* 32b */
557 #define PCM_PWR_IO_EN_LSB BIT(0) /* 8b */
559 #define PCM_CK_EN_LSB BIT(2) /* 1b */
560 #define PCM_SW_RESET_LSB BIT(15) /* 1b */
561 #define PCM_CON0_PROJECT_CODE_LSB BIT(16) /* 16b */
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H A Dsleep_def.h15 #define SPM_FLAG_DISABLE_INFRA_PDN BIT(0)
16 #define SPM_FLAG_DISABLE_DPM_PDN BIT(1)
17 #define SPM_FLAG_DISABLE_MCUPM_PDN BIT(2)
18 #define SPM_FLAG_DISABLE_DPY_PDN BIT(3)
19 #define SPM_FLAG_ENABLE_LVTS_WORKAROUND BIT(4)
20 #define SPM_FLAG_DISABLE_SYSRAM_SLEEP BIT(5)
21 #define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP BIT(6)
22 #define SPM_FLAG_DISABLE_BUS_CLK_OFF BIT(7)
23 #define SPM_FLAG_DISABLE_VCORE_DVS BIT(8)
24 #define SPM_FLAG_DISABLE_DDR_DFS BIT(9)
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H A Dpcm_def.h11 #define R12_PCM_TIMER_B BIT(0)
12 #define R12_TWAM_PMSR_DVFSRC BIT(1)
13 #define R12_KP_IRQ_B BIT(2)
14 #define R12_APWDT_EVENT_B BIT(3)
15 #define R12_APXGPT_EVENT_B BIT(4)
16 #define R12_CONN2AP_WAKEUP_B BIT(5)
17 #define R12_EINT_EVENT_B BIT(6)
18 #define R12_CONN_WDT_IRQ_B BIT(7)
19 #define R12_CCIF0_EVENT_B BIT(8)
20 #define R12_CCIF1_EVENT_B BIT(9)
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/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp15_rcc.h238 #define RCC_TZCR_TZEN BIT(0)
239 #define RCC_TZCR_MCKPROT BIT(1)
242 #define RCC_OCENSETR_HSION BIT(0)
243 #define RCC_OCENSETR_HSIKERON BIT(1)
244 #define RCC_OCENSETR_CSION BIT(4)
245 #define RCC_OCENSETR_CSIKERON BIT(5)
246 #define RCC_OCENSETR_DIGBYP BIT(7)
247 #define RCC_OCENSETR_HSEON BIT(8)
248 #define RCC_OCENSETR_HSEKERON BIT(9)
249 #define RCC_OCENSETR_HSEBYP BIT(10)
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H A Dstm32mp13_rcc.h215 #define RCC_SECCFGR_HSISEC BIT(0)
216 #define RCC_SECCFGR_CSISEC BIT(1)
217 #define RCC_SECCFGR_HSESEC BIT(2)
218 #define RCC_SECCFGR_LSISEC BIT(3)
219 #define RCC_SECCFGR_LSESEC BIT(4)
220 #define RCC_SECCFGR_PLL12SEC BIT(8)
221 #define RCC_SECCFGR_PLL3SEC BIT(9)
222 #define RCC_SECCFGR_PLL4SEC BIT(10)
223 #define RCC_SECCFGR_MPUSEC BIT(11)
224 #define RCC_SECCFGR_AXISEC BIT(12)
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H A Dstm32_uart_regs.h26 #define USART_CR1_UE BIT(0)
27 #define USART_CR1_UESM BIT(1)
28 #define USART_CR1_RE BIT(2)
29 #define USART_CR1_TE BIT(3)
30 #define USART_CR1_IDLEIE BIT(4)
31 #define USART_CR1_RXNEIE BIT(5)
32 #define USART_CR1_TCIE BIT(6)
33 #define USART_CR1_TXEIE BIT(7)
34 #define USART_CR1_PEIE BIT(8)
35 #define USART_CR1_PS BIT(9)
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H A Dstm32mp21_pwr.h62 #define PWR_CR1_VDDIO3VMEN BIT(0)
63 #define PWR_CR1_USB33VMEN BIT(2)
64 #define PWR_CR1_AVMEN BIT(4)
65 #define PWR_CR1_VDDIO3SV BIT(8)
66 #define PWR_CR1_USB33SV BIT(10)
67 #define PWR_CR1_ASV BIT(12)
68 #define PWR_CR1_VDDIO3RDY BIT(16)
69 #define PWR_CR1_USB33RDY BIT(18)
70 #define PWR_CR1_ARDY BIT(20)
71 #define PWR_CR1_VDDIOVRSEL BIT(24)
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H A Dstm32mp25_rcc.h730 #define RCC_R0CIDCFGR_CFEN BIT(0)
731 #define RCC_R0CIDCFGR_SEM_EN BIT(1)
738 #define RCC_R0SEMCR_SEM_MUTEX BIT(0)
743 #define RCC_R1CIDCFGR_CFEN BIT(0)
744 #define RCC_R1CIDCFGR_SEM_EN BIT(1)
751 #define RCC_R1SEMCR_SEM_MUTEX BIT(0)
756 #define RCC_R2CIDCFGR_CFEN BIT(0)
757 #define RCC_R2CIDCFGR_SEM_EN BIT(1)
764 #define RCC_R2SEMCR_SEM_MUTEX BIT(0)
769 #define RCC_R3CIDCFGR_CFEN BIT(0)
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H A Dstm32mp21_rcc.h685 #define RCC_R0CIDCFGR_CFEN BIT(0)
686 #define RCC_R0CIDCFGR_SEM_EN BIT(1)
693 #define RCC_R0SEMCR_SEM_MUTEX BIT(0)
698 #define RCC_R1CIDCFGR_CFEN BIT(0)
699 #define RCC_R1CIDCFGR_SEM_EN BIT(1)
706 #define RCC_R1SEMCR_SEM_MUTEX BIT(0)
711 #define RCC_R2CIDCFGR_CFEN BIT(0)
712 #define RCC_R2CIDCFGR_SEM_EN BIT(1)
719 #define RCC_R2SEMCR_SEM_MUTEX BIT(0)
724 #define RCC_R3CIDCFGR_CFEN BIT(0)
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/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dsleep_def.h11 #define SPM_FLAG_DISABLE_INFRA_PDN BIT(0)
12 #define SPM_FLAG_DISABLE_DPM_PDN BIT(1)
13 #define SPM_FLAG_DISABLE_MCUPM_PDN BIT(2)
14 #define SPM_FLAG_RESERVED_BIT_3 BIT(3)
15 #define SPM_FLAG_DISABLE_VLP_PDN BIT(4)
16 #define SPM_FLAG_DISABLE_VLPCLK_SWITCH BIT(5)
17 #define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP BIT(6)
18 #define SPM_FLAG_RESERVED_BIT_7 BIT(7)
19 #define SPM_FLAG_DISABLE_VCORE_DVS BIT(8)
20 #define SPM_FLAG_DISABLE_DDR_DFS BIT(9)
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H A Dpcm_def.h10 #define R12_PCM_TIMER_B BIT(0)
11 #define R12_TWAM_PMSR_DVFSRC_ALCO BIT(1)
12 #define R12_KP_IRQ_B BIT(2)
13 #define R12_APWDT_EVENT_B BIT(3)
14 #define R12_APXGPT_EVENT_B BIT(4)
15 #define R12_CONN2AP_WAKEUP_B BIT(5)
16 #define R12_EINT_EVENT_B BIT(6)
17 #define R12_CONN_WDT_IRQ_B BIT(7)
18 #define R12_CCIF0_EVENT_B BIT(8)
19 #define R12_CCIF1_EVENT_B BIT(9)
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H A Dmt_spm_reg.h762 #define BCLK_CG_EN_LSB BIT(0)
763 #define PROJECT_CODE_LSB BIT(16)
764 #define POWER_ON_VAL0_LSB BIT(0)
765 #define POWER_ON_VAL1_LSB BIT(0)
766 #define POWER_ON_VAL2_LSB BIT(0)
767 #define POWER_ON_VAL3_LSB BIT(0)
768 #define PCM_PWR_IO_EN_LSB BIT(0)
769 #define PCM_CK_EN_LSB BIT(2)
770 #define PCM_SW_RESET_LSB BIT(15)
771 #define PCM_CON0_PROJECT_CODE_LSB BIT(16)
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/rk3399_ARM-atf/drivers/imx/uart/
H A Dimx_uart.h12 #define IMX_UART_RXD_CHARRDY BIT(15)
13 #define IMX_UART_RXD_ERR BIT(14)
14 #define IMX_UART_RXD_OVERRUN BIT(13)
15 #define IMX_UART_RXD_FRMERR BIT(12)
16 #define IMX_UART_RXD_BRK BIT(11)
17 #define IMX_UART_RXD_PRERR BIT(10)
22 #define IMX_UART_CR1_ADEN BIT(15)
23 #define IMX_UART_CR1_ADBR BIT(14)
24 #define IMX_UART_CR1_TRDYEN BIT(13)
25 #define IMX_UART_CR1_IDEN BIT(12)
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/rk3399_ARM-atf/drivers/renesas/rcar/pfc/V3M/
H A Dpfc_init_v3m.c16 #define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
17 #define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)
18 #define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)
19 #define GPSR0_DU_DOTCLKOUT BIT(18)
20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
25 #define GPSR0_DU_DB2 BIT(12)
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/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/include/
H A Dgpc_reg.h39 #define MASK_DSM_TRIGGER_A53 BIT(31)
40 #define IRQ_SRC_A53_WUP BIT(30)
42 #define IRQ_SRC_C1 BIT(29)
43 #define IRQ_SRC_C0 BIT(28)
44 #define IRQ_SRC_C3 BIT(23)
45 #define IRQ_SRC_C2 BIT(22)
46 #define CPU_CLOCK_ON_LPM BIT(14)
47 #define A53_CLK_ON_LPM BIT(14)
48 #define MASTER0_LPM_HSK BIT(6)
49 #define MASTER1_LPM_HSK BIT(7)
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/rk3399_ARM-atf/plat/mediatek/drivers/spm/
H A Dmt_spm_common_v1.h44 #define CTRL0_SC_26M_CK_OFF BIT(0)
45 #define CTRL0_SC_VLP_BUS_CK_OFF BIT(1)
46 #define CTRL0_SC_PMIF_CK_OFF BIT(2)
47 #define CTRL0_SC_AXI_CK_OFF BIT(3)
48 #define CTRL0_SC_AXI_MEM_CK_OFF BIT(4)
49 #define CTRL0_SC_MD26M_CK_OFF BIT(5)
50 #define CTRL0_SC_MD32K_CK_OFF BIT(6)
51 #define CTRL0_SC_VLP_26M_CLK_SEL BIT(7)
52 #define CTRL0_SC_26M_CK_SEL BIT(8)
53 #define CTRL0_SC_TOP_26M_CLK_SEL BIT(9)
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/rk3399_ARM-atf/plat/imx/imx8m/imx8mm/include/
H A Dgpc_reg.h37 #define MASK_DSM_TRIGGER_A53 BIT(31)
38 #define IRQ_SRC_A53_WUP BIT(30)
40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
44 #define CPU_CLOCK_ON_LPM BIT(14)
45 #define A53_CLK_ON_LPM BIT(14)
46 #define MASTER0_LPM_HSK BIT(6)
47 #define MASTER1_LPM_HSK BIT(7)
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/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/include/
H A Dgpc_reg.h37 #define MASK_DSM_TRIGGER_A53 BIT(31)
38 #define IRQ_SRC_A53_WUP BIT(30)
40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
44 #define CPU_CLOCK_ON_LPM BIT(14)
45 #define A53_CLK_ON_LPM BIT(14)
46 #define MASTER0_LPM_HSK BIT(6)
47 #define MASTER1_LPM_HSK BIT(7)
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/rk3399_ARM-atf/plat/brcm/board/stingray/include/
H A Dusb_phy.h23 #define DRDU2_U2PLL_LOCK BIT(6U)
24 #define DRDU2_U2PLL_RESETB BIT(5U)
27 #define DRDU2_U2PLL_SUSPEND_EN BIT(0U)
30 #define DRDU2_U2IDDQ BIT(30U)
31 #define DRDU2_U2SOFT_RST_N BIT(29U)
32 #define DRDU2_U2PHY_ON_FLAG BIT(22U)
35 #define DRDU2_U2PHY_RESETB BIT(5U)
36 #define DRDU2_U2PHY_ISO BIT(4U)
37 #define DRDU2_U2AFE_BG_PWRDWNB BIT(3U)
38 #define DRDU2_U2AFE_PLL_PWRDWNB BIT(2U)
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/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/include/
H A Dgpc_reg.h37 #define MASK_DSM_TRIGGER_A53 BIT(31)
38 #define IRQ_SRC_A53_WUP BIT(30)
40 #define IRQ_SRC_C1 BIT(29)
41 #define IRQ_SRC_C0 BIT(28)
42 #define IRQ_SRC_C3 BIT(23)
43 #define IRQ_SRC_C2 BIT(22)
44 #define CPU_CLOCK_ON_LPM BIT(14)
45 #define A53_CLK_ON_LPM BIT(14)
46 #define MASTER0_LPM_HSK BIT(6)
47 #define MASTER1_LPM_HSK BIT(7)
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/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v1/
H A Dmcucfg.h22 #define MP2_CPU0_STANDBYWFE BIT(4)
23 #define MP2_CPU1_STANDBYWFE BIT(5)
29 #define sw_spark_en BIT(0)
30 #define sw_no_wait_for_q_channel BIT(1)
31 #define sw_fsm_override BIT(2)
32 #define sw_logic_pre1_pdb BIT(3)
33 #define sw_logic_pre2_pdb BIT(4)
34 #define sw_logic_pdb BIT(5)
35 #define sw_iso BIT(6)
37 #define sw_sram_isointb BIT(13)
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/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_f2sdram_manager.h17 #define FLAGOUTCLR0_F2SDRAM0_ENABLE (BIT(8))
18 #define FLAGOUTSETCLR_F2SDRAM0_ENABLE (BIT(1))
19 #define FLAGOUTSETCLR_F2SDRAM1_ENABLE (BIT(4))
20 #define FLAGOUTSETCLR_F2SDRAM2_ENABLE (BIT(7))
22 #define FLAGOUTSETCLR_F2SDRAM0_IDLEREQ (BIT(0))
23 #define FLAGOUTSETCLR_F2SDRAM1_IDLEREQ (BIT(3))
24 #define FLAGOUTSETCLR_F2SDRAM2_IDLEREQ (BIT(6))
25 #define FLAGINSTATUS_F2SDRAM0_IDLEACK (BIT(1))
26 #define FLAGINSTATUS_F2SDRAM1_IDLEACK (BIT(5))
27 #define FLAGINSTATUS_F2SDRAM2_IDLEACK (BIT(9))
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/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dmcucfg.h23 #define MP2_CPU0_STANDBYWFE BIT(4)
24 #define MP2_CPU1_STANDBYWFE BIT(5)
30 #define sw_spark_en BIT(0)
31 #define sw_no_wait_for_q_channel BIT(1)
32 #define sw_fsm_override BIT(2)
33 #define sw_logic_pre1_pdb BIT(3)
34 #define sw_logic_pre2_pdb BIT(4)
35 #define sw_logic_pdb BIT(5)
36 #define sw_iso BIT(6)
38 #define sw_sram_isointb BIT(13)
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/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dmcucfg.h23 #define MP2_CPU0_STANDBYWFE BIT(4)
24 #define MP2_CPU1_STANDBYWFE BIT(5)
30 #define sw_spark_en BIT(0)
31 #define sw_no_wait_for_q_channel BIT(1)
32 #define sw_fsm_override BIT(2)
33 #define sw_logic_pre1_pdb BIT(3)
34 #define sw_logic_pre2_pdb BIT(4)
35 #define sw_logic_pdb BIT(5)
36 #define sw_iso BIT(6)
38 #define sw_sram_isointb BIT(13)
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