Lines Matching refs:BIT
11 #define SPM_FLAG_DISABLE_INFRA_PDN BIT(0)
12 #define SPM_FLAG_DISABLE_DPM_PDN BIT(1)
13 #define SPM_FLAG_DISABLE_MCUPM_PDN BIT(2)
14 #define SPM_FLAG_RESERVED_BIT_3 BIT(3)
15 #define SPM_FLAG_DISABLE_VLP_PDN BIT(4)
16 #define SPM_FLAG_DISABLE_VLPCLK_SWITCH BIT(5)
17 #define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP BIT(6)
18 #define SPM_FLAG_RESERVED_BIT_7 BIT(7)
19 #define SPM_FLAG_DISABLE_VCORE_DVS BIT(8)
20 #define SPM_FLAG_DISABLE_DDR_DFS BIT(9)
21 #define SPM_FLAG_DISABLE_EMI_DFS BIT(10)
22 #define SPM_FLAG_DISABLE_BUS_DFS BIT(11)
23 #define SPM_FLAG_DISABLE_COMMON_SCENARIO BIT(12)
24 #define SPM_FLAG_RESERVED_BIT_13 BIT(13)
25 #define SPM_FLAG_RESERVED_BIT_14 BIT(14)
26 #define SPM_FLAG_RESERVED_BIT_15 BIT(15)
27 #define SPM_FLAG_KEEP_CSYSPWRACK_HIGH BIT(16)
28 #define SPM_FLAG_ENABLE_MT8196_IVI BIT(17)
29 #define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP BIT(18)
30 #define SPM_FLAG_RUN_COMMON_SCENARIO BIT(19)
31 #define SPM_FLAG_USE_SRCCLKENO2 BIT(20)
32 #define SPM_FLAG_ENABLE_AOV BIT(21)
33 #define SPM_FLAG_ENABLE_MD_MUMTAS BIT(22)
34 #define SPM_FLAG_ENABLE_COMMON_SODI5 BIT(23)
35 #define SPM_FLAG_ENABLE_MT8196_E1_WA BIT(24)
36 #define SPM_FLAG_ENABLE_MT8196_EMI_E1_WA BIT(25)
37 #define SPM_FLAG_VCORE_STATE BIT(26)
38 #define SPM_FLAG_VTCXO_STATE BIT(27)
39 #define SPM_FLAG_INFRA_STATE BIT(28)
40 #define SPM_FLAG_APSRC_STATE BIT(29)
41 #define SPM_FLAG_VRF18_STATE BIT(30)
42 #define SPM_FLAG_DDREN_STATE BIT(31)
45 #define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M BIT(0)
46 #define SPM_FLAG1_DISABLE_SYSPLL_OFF BIT(1)
47 #define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH BIT(2)
48 #define SPM_FLAG1_DISABLE_CSOPLU_OFF BIT(3)
49 #define SPM_FLAG1_FW_SET_CSOPLU_ON BIT(4)
50 #define SPM_FLAG1_DISABLE_EMI_CLK_TO_CSOPLU BIT(5)
51 #define SPM_FLAG1_DISABLE_NO_RESUME BIT(6)
52 #define SPM_FLAG1_RESERVED_BIT_7 BIT(7)
53 #define SPM_FLAG1_RESERVED_BIT_8 BIT(8)
54 #define SPM_FLAG1_RESERVED_BIT_9 BIT(9)
55 #define SPM_FLAG1_DISABLE_SRCLKEN_LOW BIT(10)
56 #define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH BIT(11)
57 #define SPM_FLAG1_DISABLE_TOP_26M_CK_OFF BIT(12)
58 #define SPM_FLAG1_DISABLE_PCM_26M_SWITCH BIT(13)
59 #define SPM_FLAG1_DISABLE_CKSQ_OFF BIT(14)
60 #define SPM_FLAG1_DO_DPSW_0P725V BIT(15)
61 #define SPM_FLAG1_ENABLE_ALCO_TRACE BIT(16)
62 #define SPM_FLAG1_ENABLE_SUSPEND_AVS BIT(17)
63 #define SPM_FLAG1_DISABLE_TVCORE_OFF BIT(18)
64 #define SPM_FLAG1_ENABLE_CSOPLU_OFF BIT(19)
65 #define SPM_FLAG1_DISABLE_INFRA_SRAM_SLEEP BIT(20)
66 #define SPM_FLAG1_DISABLE_AXI_MEM_CLK_OFF BIT(21)
67 #define SPM_FLAG1_RESERVED_BIT_22 BIT(22)
68 #define SPM_FLAG1_RESERVED_BIT_23 BIT(23)
69 #define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL BIT(24)
70 #define SPM_FLAG1_RESERVED_BIT_25 BIT(25)
71 #define SPM_FLAG1_RESERVED_BIT_26 BIT(26)
72 #define SPM_FLAG1_RESERVED_BIT_27 BIT(27)
73 #define SPM_FLAG1_RESERVED_BIT_28 BIT(28)
74 #define SPM_FLAG1_RESERVED_BIT_29 BIT(29)
75 #define SPM_FLAG1_ENABLE_WAKE_PROF BIT(30)
76 #define SPM_FLAG1_ENABLE_SLEEP_PROF BIT(31)
79 #define SPM_DBG_DEBUG_IDX_26M_WAKE BIT(0)
80 #define SPM_DBG_DEBUG_IDX_26M_SLEEP BIT(1)
81 #define SPM_DBG_DEBUG_IDX_INFRA_WAKE BIT(2)
82 #define SPM_DBG_DEBUG_IDX_INFRA_SLEEP BIT(3)
83 #define SPM_DBG_DEBUG_IDX_APSRC_WAKE BIT(4)
84 #define SPM_DBG_DEBUG_IDX_APSRC_SLEEP BIT(5)
85 #define SPM_DBG_DEBUG_IDX_VRF18_WAKE BIT(6)
86 #define SPM_DBG_DEBUG_IDX_VRF18_SLEEP BIT(7)
87 #define SPM_DBG_DEBUG_IDX_VCORE_WAKE BIT(8)
88 #define SPM_DBG_DEBUG_IDX_VCORE_SLEEP BIT(9)
89 #define SPM_DBG_DEBUG_IDX_DDREN_WAKE BIT(10)
90 #define SPM_DBG_DEBUG_IDX_DDREN_SLEEP BIT(11)
91 #define SPM_DBG_DEBUG_IDX_PMIC_WAKE BIT(12)
92 #define SPM_DBG_DEBUG_IDX_PMIC_SLEEP BIT(13)
93 #define SPM_DBG_DEBUG_IDX_EMI_WAKE BIT(14)
94 #define SPM_DBG_DEBUG_IDX_EMI_SLEEP BIT(15)
95 #define SPM_DBG_DEBUG_IDX_AOVBUS_WAKE BIT(16)
96 #define SPM_DBG_DEBUG_IDX_AOVBUS_SLEEP BIT(17)
97 #define SPM_DBG_DEBUG_IDX_CURRENT_IS_CM BIT(18)
98 #define SPM_DBG_DEBUG_IDX_SYSRAM_ON BIT(19)
99 #define SPM_DBG_DEBUG_IDX_WAIT_SSPM BIT(20)
100 #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP BIT(21)
101 #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON BIT(22)
102 #define SPM_DBG_DEBUG_IDX_SPM_DVFS_NO_REQ BIT(23)
103 #define SPM_DBG_DEBUG_IDX_VCORE_LP_MODE BIT(24)
104 #define SPM_DBG_DEBUG_IDX_SPM_NORMAL_WAKEUP BIT(28)
105 #define SPM_DBG_DEBUG_IDX_SPM_WAKEUP_BY_NONE BIT(29)
107 #define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP BIT(0)
108 #define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START BIT(1)
109 #define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF BIT(2)
110 #define SPM_DBG1_DEBUG_IDX_SYSPLL_ON BIT(3)
111 #define SPM_DBG1_DEBUG_IDX_VMDDRVDDQ_ON BIT(4)
112 #define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF BIT(5)
113 #define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON BIT(6)
114 #define SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_0 BIT(7)
115 #define SPM_DBG1_DEBUG_IDX_VTCXO_SLEEP_ABORT_1 BIT(8)
116 #define SPM_DBG1_DEBUG_IDX_VCORE_SLEEP_ABORT_0 BIT(9)
117 #define SPM_DBG1_DEBUG_IDX_VCORE_SLEEP_ABORT_1 BIT(10)
118 #define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_CSOPLU BIT(11)
119 #define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M BIT(12)
120 #define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K BIT(13)
121 #define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M BIT(14)
122 #define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF BIT(15)
123 #define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON BIT(16)
124 #define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW BIT(17)
125 #define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH BIT(18)
126 #define SPM_DBG1_RESERVED_BIT_19 BIT(19)
127 #define SPM_DBG1_DEBUG_IDX_CSOPLU_IS_OFF_BUT_SHOULD_ON BIT(20)
128 #define SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_LOW_ABORT BIT(21)
129 #define SPM_DBG1_DEBUG_IDX_PMIC_IRQ_ACK_HIGH_ABORT BIT(22)
130 #define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT BIT(23)
131 #define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT BIT(24)
132 #define SPM_DBG1_DEBUG_IDX_VMDDRVDDQ_OFF BIT(25)
133 #define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT BIT(26)
134 #define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT BIT(27)
135 #define SPM_DBG1_DEBUG_IDX_SPM_PMIF_CMD_RDY_ABORT BIT(28)
136 #define SPM_DBG1_DEBUG_IDX_EMI_PDN_RDY_ABORT BIT(29)
137 #define SPM_DBG1_DEBUG_IDX_LVTS_WRONG_DEVICE_ID BIT(30)
138 #define SPM_DBG1_DEBUG_IDX_DISABLE_DVFSRC BIT(31)
141 #define SPM_WDT_LATCH3_RESOURCE_STATE_AOV_INFRA_ON BIT(0)
142 #define SPM_WDT_LATCH3_RESOURCE_STATE_26M_INFRA_ON BIT(1)
143 #define SPM_WDT_LATCH3_RESOURCE_STATE_AOV_CLK_ON BIT(2)
144 #define SPM_WDT_LATCH3_RESOURCE_STATE_26M_CLK_ON BIT(3)
145 #define SPM_WDT_LATCH3_RESOURCE_STATE_AOV_EMI_ON BIT(4)
146 #define SPM_WDT_LATCH3_RESOURCE_STATE_26M_EMI_ON BIT(5)