spm/mt8196/pcm_def.h

10 #define R12_PCM_TIMER_B				BIT(0)
11 #define R12_TWAM_PMSR_DVFSRC_ALCO		BIT(1)
12 #define R12_KP_IRQ_B				BIT(2)
13 #define R12_APWDT_EVENT_B			BIT(3)
14 #define R12_APXGPT_EVENT_B			BIT(4)
15 #define R12_CONN2AP_WAKEUP_B			BIT(5)
16 #define R12_EINT_EVENT_B			BIT(6)
17 #define R12_CONN_WDT_IRQ_B			BIT(7)
18 #define R12_CCIF0_EVENT_B			BIT(8)
19 #define R12_CCIF1_EVENT_B			BIT(9)
20 #define R12_SSPM2SPM_WAKEUP_B			BIT(10)
21 #define R12_SCP2SPM_WAKEUP_B			BIT(11)
22 #define R12_ADSP2SPM_WAKEUP_B			BIT(12)
23 #define R12_PCM_WDT_WAKEUP_B			BIT(13)
24 #define R12_USB0_CDSC_B				BIT(14)
25 #define R12_USB0_POWERDWN_B			BIT(15)
26 #define R12_UART_EVENT_B			BIT(16)
27 #define R12_DEBUGTOP_FLAG_IRQ_B			BIT(17)
28 #define R12_SYS_TIMER_EVENT_B			BIT(18)
29 #define R12_EINT_EVENT_SECURE_B			BIT(19)
30 #define R12_AFE_IRQ_MCU_B			BIT(20)
31 #define R12_THERM_CTRL_EVENT_B			BIT(21)
32 #define R12_SYS_CIRQ_IRQ_B			BIT(22)
33 #define R12_PBUS_EVENT_B			BIT(23)
34 #define R12_CSYSPWREQ_B				BIT(24)
35 #define R12_MD_WDT_B				BIT(25)
36 #define R12_AP2AP_PEER_WAKEUP_B			BIT(26)
37 #define R12_SEJ_B				BIT(27)
38 #define R12_CPU_WAKEUP				BIT(28)
39 #define R12_APUSYS_WAKE_HOST_B			BIT(29)
40 #define R12_PCIE_WAKE_B				BIT(30)
41 #define R12_MSDC_WAKE_B				BIT(31)
43 #define EVENT_F26M_WAKE				BIT(0)
44 #define EVENT_F26M_SLEEP			BIT(1)
45 #define EVENT_INFRA_WAKE			BIT(2)
46 #define EVENT_INFRA_SLEEP			BIT(3)
47 #define EVENT_EMI_WAKE				BIT(4)
48 #define EVENT_EMI_SLEEP				BIT(5)
49 #define EVENT_APSRC_WAKE			BIT(6)
50 #define EVENT_APSRC_SLEEP			BIT(7)
51 #define EVENT_VRF18_WAKE			BIT(8)
52 #define EVENT_VRF18_SLEEP			BIT(9)
53 #define EVENT_DVFS_WAKE				BIT(10)
54 #define EVENT_DDREN_WAKE			BIT(11)
55 #define EVENT_DDREN_SLEEP			BIT(12)
56 #define EVENT_VCORE_WAKE			BIT(13)
57 #define EVENT_VCORE_SLEEP			BIT(14)
58 #define EVENT_PMIC_WAKE				BIT(15)
59 #define EVENT_PMIC_SLEEP			BIT(16)
60 #define EVENT_CPUEB_STATE			BIT(17)
61 #define EVENT_SSPM_STATE			BIT(18)
62 #define EVENT_DPM_STATE				BIT(19)
63 #define EVENT_SPM_LEAVE_VCORE_OFF_ACK		BIT(20)
64 #define EVENT_SW_SSPM_ADSP_SCP_MAILBOX_WAKE	BIT(21)
65 #define EVENT_SPM_LEAVE_SUSPEND_ACK		BIT(22)
66 #define EVENT_SPM_LEAVE_DEEPIDLE_ACK		BIT(23)
67 #define EVENT_CROSS_REQ_APU_l3			BIT(24)
68 #define EVENT_DFD_SOC_MTCMOS_REQ_IPIC_WAKE	BIT(25)
69 #define EVENT_AOVBUS_WAKE			BIT(26)
70 #define EVENT_AOVBUS_SLEEP			BIT(27)
73 	WAKE_SRC_STA1_PCM_TIMER = BIT(0),
74 	WAKE_SRC_STA1_TWAM_PMSR_DVFSRC = BIT(1),
75 	WAKE_SRC_STA1_KP_IRQ_B = BIT(2),
76 	WAKE_SRC_STA1_APWDT_EVENT_B = BIT(3),
77 	WAKE_SRC_STA1_APXGPT1_EVENT_B = BIT(4),
78 	WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = BIT(5),
79 	WAKE_SRC_STA1_EINT_EVENT_B = BIT(6),
80 	WAKE_SRC_STA1_CONN_WDT_IRQ_B = BIT(7),
81 	WAKE_SRC_STA1_CCIF0_EVENT_B = BIT(8),
82 	WAKE_SRC_STA1_CCIF1_EVENT_B = BIT(9),
83 	WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = BIT(10),
84 	WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = BIT(11),
85 	WAKE_SRC_STA1_SC_ADSP2SPM_WAKEUP_B = BIT(12),
86 	WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = BIT(13),
87 	WAKE_SRC_STA1_USB_CDSC_B = BIT(14),
88 	WAKE_SRC_STA1_USB_POWERDWN_B = BIT(15),
89 	WAKE_SRC_STA1_AP_UART_B = BIT(16),
90 	WAKE_SRC_STA1_DEBUGTOP_FLAG_IRQ_B = BIT(17),
91 	WAKE_SRC_STA1_SYS_TIMER_EVENT_B = BIT(18),
92 	WAKE_SRC_STA1_EINT_EVENT_SECURE_B = BIT(19),
93 	WAKE_SRC_STA1_AFE_IRQ_MCU_B = BIT(20),
94 	WAKE_SRC_STA1_THERM_CTRL_EVENT_B = BIT(21),
95 	WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = BIT(22),
96 	WAKE_SRC_STA1_PBUS_EVENT_B = BIT(23),
97 	WAKE_SRC_STA1_CSYSPWREQ_B = BIT(24),
98 	WAKE_SRC_STA1_MD1_WDT_B = BIT(25),
99 	WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = BIT(26),
100 	WAKE_SRC_STA1_SEJ_EVENT_B = BIT(27),
101 	WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = BIT(28),
102 	WAKE_SRC_STA1_APUSYS_WAKE_HOST_B = BIT(29),
103 	WAKE_SRC_STA1_PCIE_B = BIT(30),
104 	WAKE_SRC_STA1_MSDC_B = BIT(31),