Lines Matching refs:BIT
62 #define PWR_CR1_VDDIO3VMEN BIT(0)
63 #define PWR_CR1_USB33VMEN BIT(2)
64 #define PWR_CR1_AVMEN BIT(4)
65 #define PWR_CR1_VDDIO3SV BIT(8)
66 #define PWR_CR1_USB33SV BIT(10)
67 #define PWR_CR1_ASV BIT(12)
68 #define PWR_CR1_VDDIO3RDY BIT(16)
69 #define PWR_CR1_USB33RDY BIT(18)
70 #define PWR_CR1_ARDY BIT(20)
71 #define PWR_CR1_VDDIOVRSEL BIT(24)
72 #define PWR_CR1_VDDIO3VRSEL BIT(25)
73 #define PWR_CR1_GPVMO BIT(31)
76 #define PWR_CR2_MONEN BIT(0)
77 #define PWR_CR2_VBATL BIT(8)
78 #define PWR_CR2_VBATH BIT(9)
79 #define PWR_CR2_TEMPL BIT(10)
80 #define PWR_CR2_TEMPH BIT(11)
83 #define PWR_CR3_PVDEN BIT(0)
84 #define PWR_CR3_PVDO BIT(8)
87 #define PWR_CR7_VDDIO2VMEN BIT(0)
88 #define PWR_CR7_VDDIO2SV BIT(8)
89 #define PWR_CR7_VDDIO2RDY BIT(16)
90 #define PWR_CR7_VDDIO2VRSEL BIT(24)
91 #define PWR_CR7_VDDIO2VRSTBY BIT(25)
94 #define PWR_CR8_VDDIO1VMEN BIT(0)
95 #define PWR_CR8_VDDIO1SV BIT(8)
96 #define PWR_CR8_VDDIO1RDY BIT(16)
97 #define PWR_CR8_VDDIO1VRSEL BIT(24)
98 #define PWR_CR8_VDDIO1VRSTBY BIT(25)
101 #define PWR_CR9_BKPRBSEN BIT(0)
111 #define PWR_CR11_DDRRETDIS BIT(0)
114 #define PWR_BDCR_DBP BIT(0)
117 #define PWR_CPU1CR_PDDS_D2 BIT(0)
118 #define PWR_CPU1CR_PDDS_D1 BIT(1)
119 #define PWR_CPU1CR_VBF BIT(4)
120 #define PWR_CPU1CR_STOPF BIT(5)
121 #define PWR_CPU1CR_SBF BIT(6)
122 #define PWR_CPU1CR_SBF_D1 BIT(7)
123 #define PWR_CPU1CR_CSSF BIT(9)
124 #define PWR_CPU1CR_STANDBYWFIL2 BIT(15)
125 #define PWR_CPU1CR_LPDS_D1 BIT(16)
126 #define PWR_CPU1CR_LVDS_D1 BIT(17)
129 #define PWR_CPU2CR_PDDS_D2 BIT(0)
130 #define PWR_CPU2CR_VBF BIT(4)
131 #define PWR_CPU2CR_STOPF BIT(5)
132 #define PWR_CPU2CR_SBF BIT(6)
133 #define PWR_CPU2CR_SBF_D2 BIT(7)
134 #define PWR_CPU2CR_CSSF BIT(9)
135 #define PWR_CPU2CR_DEEPSLEEP BIT(15)
136 #define PWR_CPU2CR_LPDS_D2 BIT(16)
137 #define PWR_CPU2CR_LVDS_D2 BIT(17)
140 #define PWR_D1CR_LPCFG_D1 BIT(0)
145 #define PWR_D2CR_LPCFG_D2 BIT(0)
154 #define PWR_WKUPCR1_WKUPC BIT(0)
155 #define PWR_WKUPCR1_WKUPP BIT(8)
158 #define PWR_WKUPCR1_WKUPENCPU1 BIT(16)
159 #define PWR_WKUPCR1_WKUPENCPU2 BIT(17)
160 #define PWR_WKUPCR1_WKUPF BIT(31)
163 #define PWR_WKUPCR2_WKUPC BIT(0)
164 #define PWR_WKUPCR2_WKUPP BIT(8)
167 #define PWR_WKUPCR2_WKUPENCPU1 BIT(16)
168 #define PWR_WKUPCR2_WKUPENCPU2 BIT(17)
169 #define PWR_WKUPCR2_WKUPF BIT(31)
172 #define PWR_WKUPCR3_WKUPC BIT(0)
173 #define PWR_WKUPCR3_WKUPP BIT(8)
176 #define PWR_WKUPCR3_WKUPENCPU1 BIT(16)
177 #define PWR_WKUPCR3_WKUPENCPU2 BIT(17)
178 #define PWR_WKUPCR3_WKUPF BIT(31)
181 #define PWR_WKUPCR4_WKUPC BIT(0)
182 #define PWR_WKUPCR4_WKUPP BIT(8)
185 #define PWR_WKUPCR4_WKUPENCPU1 BIT(16)
186 #define PWR_WKUPCR4_WKUPENCPU2 BIT(17)
187 #define PWR_WKUPCR4_WKUPF BIT(31)
190 #define PWR_WKUPCR5_WKUPC BIT(0)
191 #define PWR_WKUPCR5_WKUPP BIT(8)
194 #define PWR_WKUPCR5_WKUPENCPU1 BIT(16)
195 #define PWR_WKUPCR5_WKUPENCPU2 BIT(17)
196 #define PWR_WKUPCR5_WKUPF BIT(31)
199 #define PWR_WKUPCR6_WKUPC BIT(0)
200 #define PWR_WKUPCR6_WKUPP BIT(8)
203 #define PWR_WKUPCR6_WKUPENCPU1 BIT(16)
204 #define PWR_WKUPCR6_WKUPENCPU2 BIT(17)
205 #define PWR_WKUPCR6_WKUPF BIT(31)
208 #define PWR_RSECCFGR_RSEC0 BIT(0)
209 #define PWR_RSECCFGR_RSEC1 BIT(1)
210 #define PWR_RSECCFGR_RSEC2 BIT(2)
211 #define PWR_RSECCFGR_RSEC3 BIT(3)
212 #define PWR_RSECCFGR_RSEC4 BIT(4)
213 #define PWR_RSECCFGR_RSEC5 BIT(5)
214 #define PWR_RSECCFGR_RSEC6 BIT(6)
217 #define PWR_RPRIVCFGR_RPRIV0 BIT(0)
218 #define PWR_RPRIVCFGR_RPRIV1 BIT(1)
219 #define PWR_RPRIVCFGR_RPRIV2 BIT(2)
220 #define PWR_RPRIVCFGR_RPRIV3 BIT(3)
221 #define PWR_RPRIVCFGR_RPRIV4 BIT(4)
222 #define PWR_RPRIVCFGR_RPRIV5 BIT(5)
223 #define PWR_RPRIVCFGR_RPRIV6 BIT(6)
226 #define PWR_R0CIDCFGR_CFEN BIT(0)
231 #define PWR_R1CIDCFGR_CFEN BIT(0)
236 #define PWR_R2CIDCFGR_CFEN BIT(0)
241 #define PWR_R3CIDCFGR_CFEN BIT(0)
246 #define PWR_R4CIDCFGR_CFEN BIT(0)
251 #define PWR_R5CIDCFGR_CFEN BIT(0)
256 #define PWR_R6CIDCFGR_CFEN BIT(0)
261 #define PWR_WIOSECCFGR_WIOSEC1 BIT(0)
262 #define PWR_WIOSECCFGR_WIOSEC2 BIT(1)
263 #define PWR_WIOSECCFGR_WIOSEC3 BIT(2)
264 #define PWR_WIOSECCFGR_WIOSEC4 BIT(3)
265 #define PWR_WIOSECCFGR_WIOSEC5 BIT(4)
266 #define PWR_WIOSECCFGR_WIOSEC6 BIT(5)
269 #define PWR_WIOPRIVCFGR_WIOPRIV1 BIT(0)
270 #define PWR_WIOPRIVCFGR_WIOPRIV2 BIT(1)
271 #define PWR_WIOPRIVCFGR_WIOPRIV3 BIT(2)
272 #define PWR_WIOPRIVCFGR_WIOPRIV4 BIT(3)
273 #define PWR_WIOPRIVCFGR_WIOPRIV5 BIT(4)
274 #define PWR_WIOPRIVCFGR_WIOPRIV6 BIT(5)
277 #define PWR_WIO1CIDCFGR_CFEN BIT(0)
278 #define PWR_WIO1CIDCFGR_SEM_EN BIT(1)
281 #define PWR_WIO1CIDCFGR_SEMWLC0 BIT(16)
282 #define PWR_WIO1CIDCFGR_SEMWLC1 BIT(17)
283 #define PWR_WIO1CIDCFGR_SEMWLC2 BIT(18)
284 #define PWR_WIO1CIDCFGR_SEMWLC3 BIT(19)
285 #define PWR_WIO1CIDCFGR_SEMWLC4 BIT(20)
286 #define PWR_WIO1CIDCFGR_SEMWLC5 BIT(21)
287 #define PWR_WIO1CIDCFGR_SEMWLC6 BIT(22)
288 #define PWR_WIO1CIDCFGR_SEMWLC7 BIT(23)
291 #define PWR_WIO1SEMCR_SEM_MUTEX BIT(0)
296 #define PWR_WIO2CIDCFGR_CFEN BIT(0)
297 #define PWR_WIO2CIDCFGR_SEM_EN BIT(1)
300 #define PWR_WIO2CIDCFGR_SEMWLC0 BIT(16)
301 #define PWR_WIO2CIDCFGR_SEMWLC1 BIT(17)
302 #define PWR_WIO2CIDCFGR_SEMWLC2 BIT(18)
303 #define PWR_WIO2CIDCFGR_SEMWLC3 BIT(19)
304 #define PWR_WIO2CIDCFGR_SEMWLC4 BIT(20)
305 #define PWR_WIO2CIDCFGR_SEMWLC5 BIT(21)
306 #define PWR_WIO2CIDCFGR_SEMWLC6 BIT(22)
307 #define PWR_WIO2CIDCFGR_SEMWLC7 BIT(23)
310 #define PWR_WIO2SEMCR_SEM_MUTEX BIT(0)
315 #define PWR_WIO3CIDCFGR_CFEN BIT(0)
316 #define PWR_WIO3CIDCFGR_SEM_EN BIT(1)
319 #define PWR_WIO3CIDCFGR_SEMWLC0 BIT(16)
320 #define PWR_WIO3CIDCFGR_SEMWLC1 BIT(17)
321 #define PWR_WIO3CIDCFGR_SEMWLC2 BIT(18)
322 #define PWR_WIO3CIDCFGR_SEMWLC3 BIT(19)
323 #define PWR_WIO3CIDCFGR_SEMWLC4 BIT(20)
324 #define PWR_WIO3CIDCFGR_SEMWLC5 BIT(21)
325 #define PWR_WIO3CIDCFGR_SEMWLC6 BIT(22)
326 #define PWR_WIO3CIDCFGR_SEMWLC7 BIT(23)
329 #define PWR_WIO3SEMCR_SEM_MUTEX BIT(0)
334 #define PWR_WIO4CIDCFGR_CFEN BIT(0)
335 #define PWR_WIO4CIDCFGR_SEM_EN BIT(1)
338 #define PWR_WIO4CIDCFGR_SEMWLC0 BIT(16)
339 #define PWR_WIO4CIDCFGR_SEMWLC1 BIT(17)
340 #define PWR_WIO4CIDCFGR_SEMWLC2 BIT(18)
341 #define PWR_WIO4CIDCFGR_SEMWLC3 BIT(19)
342 #define PWR_WIO4CIDCFGR_SEMWLC4 BIT(20)
343 #define PWR_WIO4CIDCFGR_SEMWLC5 BIT(21)
344 #define PWR_WIO4CIDCFGR_SEMWLC6 BIT(22)
345 #define PWR_WIO4CIDCFGR_SEMWLC7 BIT(23)
348 #define PWR_WIO4SEMCR_SEM_MUTEX BIT(0)
353 #define PWR_WIO5CIDCFGR_CFEN BIT(0)
354 #define PWR_WIO5CIDCFGR_SEM_EN BIT(1)
357 #define PWR_WIO5CIDCFGR_SEMWLC0 BIT(16)
358 #define PWR_WIO5CIDCFGR_SEMWLC1 BIT(17)
359 #define PWR_WIO5CIDCFGR_SEMWLC2 BIT(18)
360 #define PWR_WIO5CIDCFGR_SEMWLC3 BIT(19)
361 #define PWR_WIO5CIDCFGR_SEMWLC4 BIT(20)
362 #define PWR_WIO5CIDCFGR_SEMWLC5 BIT(21)
363 #define PWR_WIO5CIDCFGR_SEMWLC6 BIT(22)
364 #define PWR_WIO5CIDCFGR_SEMWLC7 BIT(23)
367 #define PWR_WIO5SEMCR_SEM_MUTEX BIT(0)
372 #define PWR_WIO6CIDCFGR_CFEN BIT(0)
373 #define PWR_WIO6CIDCFGR_SEM_EN BIT(1)
376 #define PWR_WIO6CIDCFGR_SEMWLC0 BIT(16)
377 #define PWR_WIO6CIDCFGR_SEMWLC1 BIT(17)
378 #define PWR_WIO6CIDCFGR_SEMWLC2 BIT(18)
379 #define PWR_WIO6CIDCFGR_SEMWLC3 BIT(19)
380 #define PWR_WIO6CIDCFGR_SEMWLC4 BIT(20)
381 #define PWR_WIO6CIDCFGR_SEMWLC5 BIT(21)
382 #define PWR_WIO6CIDCFGR_SEMWLC6 BIT(22)
383 #define PWR_WIO6CIDCFGR_SEMWLC7 BIT(23)
386 #define PWR_WIO6SEMCR_SEM_MUTEX BIT(0)
391 #define PWR_CPU1D1SR_HOLD_BOOT BIT(0)
398 #define PWR_CPU2D2SR_HOLD_BOOT BIT(0)
399 #define PWR_CPU2D2SR_WFBEN BIT(1)
406 #define PWR_DBGR_VDDIOKRETRAM BIT(16)
407 #define PWR_DBGR_VDDIOKBKPRAM BIT(17)