Lines Matching refs:BIT

546 #define BCLK_CG_EN_LSB BIT(0) /* 1b */
547 #define PROJECT_CODE_LSB BIT(16) /* 16b */
549 #define POWER_ON_VAL0_LSB BIT(0) /* 32b */
551 #define POWER_ON_VAL1_LSB BIT(0) /* 32b */
553 #define POWER_ON_VAL2_LSB BIT(0) /* 32b */
555 #define POWER_ON_VAL3_LSB BIT(0) /* 32b */
557 #define PCM_PWR_IO_EN_LSB BIT(0) /* 8b */
559 #define PCM_CK_EN_LSB BIT(2) /* 1b */
560 #define PCM_SW_RESET_LSB BIT(15) /* 1b */
561 #define PCM_CON0_PROJECT_CODE_LSB BIT(16) /* 16b */
563 #define REG_SPM_APB_INTERNAL_EN_LSB BIT(3) /* 1b */
564 #define REG_PCM_TIMER_EN_LSB BIT(5) /* 1b */
565 #define REG_PCM_WDT_EN_LSB BIT(8) /* 1b */
566 #define REG_PCM_WDT_WAKE_LSB BIT(9) /* 1b */
567 #define REG_SSPM_APB_P2P_EN_LSB BIT(10) /* 1b */
568 #define REG_MCUPM_APB_P2P_EN_LSB BIT(11) /* 1b */
569 #define REG_RSV_APB_P2P_EN_LSB BIT(12) /* 1b */
570 #define RG_PCM_IRQ_MSK_LSB BIT(15) /* 1b */
571 #define PCM_CON1_PROJECT_CODE_LSB BIT(16) /* 16b */
573 #define REG_SRAM_ISO_ACTIVE_LSB BIT(0) /* 8b */
574 #define REG_SRAM_SLP2ISO_TIME_LSB BIT(8) /* 8b */
575 #define REG_SPM_SRAM_CTRL_MUX_LSB BIT(16) /* 1b */
576 #define REG_SRAM_SLEEP_TIME_LSB BIT(24) /* 8b */
578 #define REG_SPM_LOCK_INFRA_DCM_LSB BIT(0) /* 1b */
579 #define REG_CXO32K_REMOVE_EN_LSB BIT(1) /* 1b */
580 #define REG_SPM_LEAVE_SUSPEND_MERGE_MASK_LSB BIT(4) /* 3b */
581 #define REG_SRCLKENO0_SRC_MASK_B_LSB BIT(8) /* 8b */
582 #define REG_SRCLKENO1_SRC_MASK_B_LSB BIT(16) /* 8b */
583 #define REG_SRCLKENO2_SRC_MASK_B_LSB BIT(24) /* 8b */
587 #define SPM_SW_RST_CON_LSB BIT(0) /* 16b */
588 #define SPM_SW_RST_CON_PROJECT_CODE_LSB BIT(16) /* 16b */
590 #define SPM_SW_RST_CON_SET_LSB BIT(0) /* 16b */
591 #define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB BIT(16) /* 16b */
593 #define SPM_SW_RST_CON_CLR_LSB BIT(0) /* 16b */
594 #define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB BIT(16) /* 16b */
596 #define SPM_SEC_READ_MASK_LSB BIT(0) /* 1b */
598 #define SPM_ONE_TIME_LOCK_L_LSB BIT(0) /* 32b */
600 #define SPM_ONE_TIME_LOCK_M_LSB BIT(0) /* 32b */
602 #define SPM_ONE_TIME_LOCK_H_LSB BIT(0) /* 32b */
604 #define REG_SSPM_26M_CK_SEL_LSB BIT(0) /* 1b */
605 #define REG_SSPM_DCM_EN_LSB BIT(1) /* 1b */
607 #define REG_SCP_26M_CK_SEL_LSB BIT(0) /* 1b */
608 #define REG_SCP_DCM_EN_LSB BIT(1) /* 1b */
609 #define SCP_SECURE_VREQ_MASK_LSB BIT(2) /* 1b */
610 #define SCP_SLP_REQ_LSB BIT(3) /* 1b */
611 #define SCP_SLP_ACK_LSB BIT(4) /* 1b */
613 #define SPM_SWINT_LSB BIT(0) /* 32b */
615 #define SPM_SWINT_SET_LSB BIT(0) /* 32b */
617 #define SPM_SWINT_CLR_LSB BIT(0) /* 32b */
619 #define REG_CPU_WAKEUP_LSB BIT(0) /* 1b */
621 #define REG_SPM_IRQ_MASK_LSB BIT(0) /* 32b */
623 #define MD32PCM_CTRL0_LSB BIT(0) /* 32b */
625 #define MD32PCM_CTRL1_LSB BIT(0) /* 32b */
627 #define MD32PCM_CTRL2_LSB BIT(0) /* 32b */
629 #define MD32PCM_CTRL3_LSB BIT(0) /* 32b */
631 #define MD32PCM_STA0_LSB BIT(0) /* 32b */
633 #define PCM_IRQ_LSB BIT(3) /* 1b */
635 #define MD32PCM_WAKEUP_STA_LSB BIT(0) /* 32b */
637 #define MD32PCM_EVENT_STA_LSB BIT(0) /* 32b */
639 #define SRCLKEN_RC_ERR_INT_LSB BIT(0) /* 1b */
640 #define SPM_TIMEOUT_WAKEUP_0_LSB BIT(1) /* 1b */
641 #define SPM_TIMEOUT_WAKEUP_1_LSB BIT(2) /* 1b */
642 #define SPM_TIMEOUT_WAKEUP_2_LSB BIT(3) /* 1b */
643 #define DVFSRC_IRQ_LSB BIT(4) /* 1b */
644 #define TWAM_IRQ_B_LSB BIT(5) /* 1b */
645 #define SPM_ACK_CHK_WAKEUP_0_LSB BIT(6) /* 1b */
646 #define SPM_ACK_CHK_WAKEUP_1_LSB BIT(7) /* 1b */
647 #define SPM_ACK_CHK_WAKEUP_2_LSB BIT(8) /* 1b */
648 #define SPM_ACK_CHK_WAKEUP_3_LSB BIT(9) /* 1b */
649 #define SPM_ACK_CHK_WAKEUP_ALL_LSB BIT(10) /* 1b */
650 #define VLP_BUS_TIMEOUT_IRQ_LSB BIT(11) /* 1b */
651 #define PCM_TIMER_EVENT_LSB BIT(16) /* 1b */
652 #define PMIC_EINT_OUT_LSB BIT(19) /* 2b */
653 #define PMIC_IRQ_ACK_LSB BIT(30) /* 1b */
654 #define PMIC_SCP_IRQ_LSB BIT(31) /* 1b */
656 #define PCM_CK_SEL_O_LSB BIT(0) /* 4b */
657 #define EXT_SRC_STA_LSB BIT(4) /* 3b */
658 #define CK_SLEEP_EN_LSB BIT(8) /* 1b */
659 #define SPM_SRAM_CTRL_CK_SEL_LSB BIT(9) /* 1b */
661 #define MD32PCM_HALT_LSB BIT(0) /* 1b */
662 #define MD32PCM_GATED_LSB BIT(1) /* 1b */
664 #define MON_PC_LSB BIT(0) /* 32b */
666 #define REG_WFI_OP_LSB BIT(0) /* 1b */
667 #define REG_WFI_TYPE_LSB BIT(1) /* 1b */
668 #define REG_MP0_CPUTOP_IDLE_MASK_LSB BIT(2) /* 1b */
669 #define REG_MP1_CPUTOP_IDLE_MASK_LSB BIT(3) /* 1b */
670 #define REG_MCUSYS_IDLE_MASK_LSB BIT(4) /* 1b */
671 #define REG_CSYSPWRUP_REQ_MASK_LSB BIT(5) /* 1b */
672 #define WFI_AF_SEL_LSB BIT(16) /* 8b */
673 #define CPU_SLEEP_WFI_LSB BIT(31) /* 1b */
675 #define CPU_WFI_EN_LSB BIT(0) /* 8b */
677 #define CPU_WFI_EN_SET_LSB BIT(0) /* 8b */
679 #define CPU_WFI_EN_CLR_LSB BIT(0) /* 8b */
681 #define EXT_INT_WAKEUP_REQ_LSB BIT(0) /* 10b */
683 #define EXT_INT_WAKEUP_REQ_SET_LSB BIT(0) /* 10b */
685 #define EXT_INT_WAKEUP_REQ_CLR_LSB BIT(0) /* 10b */
687 #define MCUSYS_DDREN_LSB BIT(0) /* 8b */
688 #define ARMBUS_IDLE_TO_26M_LSB BIT(8) /* 1b */
689 #define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB BIT(9) /* 1b */
690 #define MP0_CPU_IDLE_TO_PWR_OFF_LSB BIT(16) /* 8b */
692 #define MP0_SPMC_PWR_ON_ACK_CPU0_LSB BIT(0) /* 1b */
693 #define MP0_SPMC_PWR_ON_ACK_CPU1_LSB BIT(1) /* 1b */
694 #define MP0_SPMC_PWR_ON_ACK_CPU2_LSB BIT(2) /* 1b */
695 #define MP0_SPMC_PWR_ON_ACK_CPU3_LSB BIT(3) /* 1b */
696 #define MP0_SPMC_PWR_ON_ACK_CPU4_LSB BIT(4) /* 1b */
697 #define MP0_SPMC_PWR_ON_ACK_CPU5_LSB BIT(5) /* 1b */
698 #define MP0_SPMC_PWR_ON_ACK_CPU6_LSB BIT(6) /* 1b */
699 #define MP0_SPMC_PWR_ON_ACK_CPU7_LSB BIT(7) /* 1b */
700 #define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB BIT(8) /* 1b */
701 #define MCUSYS_SPMC_PWR_ON_ACK_LSB BIT(9) /* 1b */
703 #define SW2SPM_WAKEUP_LSB BIT(0) /* 4b */
705 #define SW2SPM_WAKEUP_SET_LSB BIT(0) /* 4b */
707 #define SW2SPM_WAKEUP_CLR_LSB BIT(0) /* 4b */
709 #define SW2SPM_MAILBOX_0_LSB BIT(0) /* 32b */
711 #define SW2SPM_MAILBOX_1_LSB BIT(0) /* 32b */
713 #define SW2SPM_MAILBOX_2_LSB BIT(0) /* 32b */
715 #define SW2SPM_MAILBOX_3_LSB BIT(0) /* 32b */
717 #define SPM2SW_MAILBOX_0_LSB BIT(0) /* 32b */
719 #define SPM2SW_MAILBOX_1_LSB BIT(0) /* 32b */
721 #define SPM2SW_MAILBOX_2_LSB BIT(0) /* 32b */
723 #define SPM2SW_MAILBOX_3_LSB BIT(0) /* 32b */
725 #define SPM2MCUPM_SW_RST_B_LSB BIT(0) /* 1b */
726 #define SPM2MCUPM_SW_INT_LSB BIT(1) /* 1b */
727 #define MCUPM_WFI_LSB BIT(16) /* 1b */
729 #define MCUSYS_SPMC_PWR_ON_LSB BIT(2) /* 1b */
730 #define MCUSYS_SPMC_RESET_PWRON_CONFIG_LSB BIT(5) /* 1b */
731 #define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB BIT(31) /* 1b */
733 #define MP0_SPMC_PWR_ON_CPUTOP_LSB BIT(2) /* 1b */
734 #define MP0_SPMC_RESET_PWRON_CONFIG_CPUTOP_LSB BIT(5) /* 1b */
735 #define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB BIT(31) /* 1b */
737 #define MP0_SPMC_PWR_ON_CPU0_LSB BIT(2) /* 1b */
738 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU0_LSB BIT(5) /* 1b */
739 #define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB BIT(31) /* 1b */
741 #define MP0_SPMC_PWR_ON_CPU1_LSB BIT(2) /* 1b */
742 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU1_LSB BIT(5) /* 1b */
743 #define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB BIT(31) /* 1b */
745 #define MP0_SPMC_PWR_ON_CPU2_LSB BIT(2) /* 1b */
746 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU2_LSB BIT(5) /* 1b */
747 #define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB BIT(31) /* 1b */
749 #define MP0_SPMC_PWR_ON_CPU3_LSB BIT(2) /* 1b */
750 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU3_LSB BIT(5) /* 1b */
751 #define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB BIT(31) /* 1b */
753 #define MP0_SPMC_PWR_ON_CPU4_LSB BIT(2) /* 1b */
754 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU4_LSB BIT(5) /* 1b */
755 #define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB BIT(31) /* 1b */
757 #define MP0_SPMC_PWR_ON_CPU5_LSB BIT(2) /* 1b */
758 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU5_LSB BIT(5) /* 1b */
759 #define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB BIT(31) /* 1b */
761 #define MP0_SPMC_PWR_ON_CPU6_LSB BIT(2) /* 1b */
762 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU6_LSB BIT(5) /* 1b */
763 #define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB BIT(31) /* 1b */
765 #define MP0_SPMC_PWR_ON_CPU7_LSB BIT(2) /* 1b */
766 #define MP0_SPMC_RESET_PWRON_CONFIG_CPU7_LSB BIT(5) /* 1b */
767 #define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB BIT(31) /* 1b */
769 #define CPUEB_STATE_VALID_LSB BIT(0) /* 1b */
770 #define REQ_PWR_ON_LSB BIT(1) /* 1b */
771 #define REQ_MEM_RET_LSB BIT(2) /* 1b */
772 #define RESET_PWR_ON_LSB BIT(4) /* 1b */
773 #define RESET_MEM_RET_LSB BIT(5) /* 1b */
774 #define CPUEB_STATE_FINISH_ACK_LSB BIT(31) /* 1b */
776 #define P2P_TX_STA_LSB BIT(0) /* 32b */
778 #define REG_P2P_TX_ERROR_FLAG_EN_LSB BIT(0) /* 1b */
780 #define SC_HW_S1_REQ_LSB BIT(0) /* 1b */
781 #define REG_HW_S1_ACK_MASK_LSB BIT(4) /* 4b */
782 #define SC_HW_S1_ACK_LSB BIT(8) /* 4b */
784 #define REG_DPM_WB_EN_LSB BIT(0) /* 1b */
786 #define SPM_ACK_CHK_TIMER_VAL_3_LSB BIT(0) /* 16b */
787 #define SPM_ACK_CHK_TIMER_3_LSB BIT(16) /* 16b */
789 #define SPM_ACK_CHK_STA_3_LSB BIT(0) /* 32b */
791 #define SPM_PWRAP_CON_LSB BIT(0) /* 32b */
793 #define SPM_PWRAP_CON_STA_LSB BIT(0) /* 32b */
795 #define SPM_PMIC_SPMI_CMD_LSB BIT(0) /* 2b */
796 #define SPM_PMIC_SPMI_SLAVEID_LSB BIT(2) /* 4b */
797 #define SPM_PMIC_SPMI_PMIFID_LSB BIT(6) /* 1b */
798 #define SPM_PMIC_SPMI_DBCNT_LSB BIT(7) /* 1b */
800 #define SPM_PWRAP_CMD0_LSB BIT(0) /* 32b */
802 #define SPM_PWRAP_CMD1_LSB BIT(0) /* 32b */
804 #define SPM_PWRAP_CMD2_LSB BIT(0) /* 32b */
806 #define SPM_PWRAP_CMD3_LSB BIT(0) /* 32b */
808 #define SPM_PWRAP_CMD4_LSB BIT(0) /* 32b */
810 #define SPM_PWRAP_CMD5_LSB BIT(0) /* 32b */
812 #define SPM_PWRAP_CMD6_LSB BIT(0) /* 32b */
814 #define SPM_PWRAP_CMD7_LSB BIT(0) /* 32b */
816 #define SPM_PWRAP_CMD8_LSB BIT(0) /* 32b */
818 #define SPM_PWRAP_CMD9_LSB BIT(0) /* 32b */
820 #define SPM_PWRAP_CMD10_LSB BIT(0) /* 32b */
822 #define SPM_PWRAP_CMD11_LSB BIT(0) /* 32b */
824 #define SPM_PWRAP_CMD12_LSB BIT(0) /* 32b */
826 #define SPM_PWRAP_CMD13_LSB BIT(0) /* 32b */
828 #define SPM_PWRAP_CMD14_LSB BIT(0) /* 32b */
830 #define SPM_PWRAP_CMD15_LSB BIT(0) /* 32b */
832 #define SPM_PWRAP_CMD16_LSB BIT(0) /* 32b */
834 #define SPM_PWRAP_CMD17_LSB BIT(0) /* 32b */
836 #define SPM_PWRAP_CMD18_LSB BIT(0) /* 32b */
838 #define SPM_PWRAP_CMD19_LSB BIT(0) /* 32b */
840 #define SPM_PWRAP_CMD20_LSB BIT(0) /* 32b */
842 #define SPM_PWRAP_CMD21_LSB BIT(0) /* 32b */
844 #define SPM_PWRAP_CMD22_LSB BIT(0) /* 32b */
846 #define SPM_PWRAP_CMD23_LSB BIT(0) /* 32b */
848 #define SPM_PWRAP_CMD24_LSB BIT(0) /* 32b */
850 #define SPM_PWRAP_CMD25_LSB BIT(0) /* 32b */
852 #define SPM_PWRAP_CMD26_LSB BIT(0) /* 32b */
854 #define SPM_PWRAP_CMD27_LSB BIT(0) /* 32b */
856 #define SPM_PWRAP_CMD28_LSB BIT(0) /* 32b */
858 #define SPM_PWRAP_CMD29_LSB BIT(0) /* 32b */
860 #define SPM_PWRAP_CMD30_LSB BIT(0) /* 32b */
862 #define SPM_PWRAP_CMD31_LSB BIT(0) /* 32b */
864 #define DVFSRC_EVENT_LSB BIT(0) /* 32b */
866 #define FORCE_DVFS_LEVEL_LSB BIT(0) /* 32b */
868 #define TARGET_DVFS_LEVEL_LSB BIT(0) /* 32b */
870 #define SPM_DFS_LEVEL_LSB BIT(0) /* 16b */
871 #define SPM_DVS_LEVEL_LSB BIT(16) /* 16b */
873 #define SPM_DVFS_LEVEL_LSB BIT(0) /* 32b */
875 #define SPM_DVFS_OPP_LSB BIT(0) /* 5b */
877 #define SPM2MM_FORCE_ULTRA_LSB BIT(0) /* 1b */
878 #define SPM2MM_DBL_OSTD_ACT_LSB BIT(1) /* 1b */
879 #define SPM2MM_ULTRAREQ_LSB BIT(2) /* 1b */
880 #define SPM2MD_ULTRAREQ_LSB BIT(3) /* 1b */
881 #define SPM2ISP_ULTRAREQ_LSB BIT(4) /* 1b */
882 #define SPM2ISP_ULTRAACK_D2T_LSB BIT(18) /* 1b */
883 #define SPM2MM_ULTRAACK_D2T_LSB BIT(19) /* 1b */
884 #define SPM2MD_ULTRAACK_D2T_LSB BIT(20) /* 1b */
886 #define SPM_DVFS_FORCE_ENABLE_LSB BIT(2) /* 1b */
887 #define FORCE_DVFS_WAKE_LSB BIT(3) /* 1b */
888 #define SPM_DVFSRC_ENABLE_LSB BIT(4) /* 1b */
889 #define DVFSRC_WAKEUP_EVENT_MASK_LSB BIT(6) /* 1b */
890 #define SPM2RC_EVENT_ABORT_LSB BIT(7) /* 1b */
891 #define DVFSRC_LEVEL_ACK_LSB BIT(8) /* 1b */
893 #define VSRAM_GEAR_REQ_LSB BIT(0) /* 1b */
894 #define VSRAM_GEAR_RDY_LSB BIT(4) /* 1b */
895 #define VSRAM_VAL_LEVEL_LSB BIT(16) /* 8b */
897 #define SPM_PMIF_VALID_LSB BIT(0) /* 1b */
898 #define SPM_PMIF_ACK_LSB BIT(4) /* 1b */
900 #define DPSW_VLOGIC_REQ_LSB BIT(0) /* 1b */
901 #define DPSW_VLOGIC_ISO_LSB BIT(4) /* 1b */
902 #define DPSW_VLOGIC_ACK_LSB BIT(8) /* 1b */
903 #define DPSW_VSRAM_ACK_LSB BIT(12) /* 1b */
905 #define ULPOSC_EN_LSB BIT(0) /* 1b */
906 #define ULPOSC_RST_LSB BIT(1) /* 1b */
907 #define ULPOSC_CG_EN_LSB BIT(2) /* 1b */
908 #define ULPOSC_CLK_SEL_LSB BIT(3) /* 1b */
910 #define AP_MDSMSRC_REQ_LSB BIT(0) /* 1b */
911 #define AP_L1SMSRC_REQ_LSB BIT(1) /* 1b */
912 #define AP2MD_PEER_WAKEUP_LSB BIT(3) /* 1b */
913 #define AP_MDSMSRC_ACK_LSB BIT(4) /* 1b */
914 #define AP_L1SMSRC_ACK_LSB BIT(5) /* 1b */
916 #define SPM2MD_SWITCH_CTRL_LSB BIT(0) /* 10b */
918 #define SPM_AP_26M_RDY_LSB BIT(0) /* 1b */
919 #define SPM2RC_DMY_CTRL_LSB BIT(2) /* 6b */
920 #define RC2SPM_SRCCLKENO_0_ACK_LSB BIT(16) /* 1b */
922 #define SPM2GPUEB_SW_RST_B_LSB BIT(0) /* 1b */
923 #define SPM2GPUEB_SW_INT_LSB BIT(1) /* 1b */
924 #define SC_MFG_PLL_EN_LSB BIT(4) /* 1b */
925 #define GPUEB_WFI_LSB BIT(16) /* 1b */
927 #define RPC_SRAM_CTRL_MUX_SEL_LSB BIT(0) /* 1b */
928 #define APU_VCORE_OFF_ISO_EN_LSB BIT(1) /* 1b */
929 #define APU_ARE_REQ_LSB BIT(4) /* 1b */
930 #define APU_ARE_ACK_LSB BIT(8) /* 1b */
931 #define APU_ACTIVE_STATE_LSB BIT(9) /* 1b */
932 #define APU_AOV_WAKEUP_LSB BIT(16) /* 1b */
934 #define AOC_EFUSE_EN_LSB BIT(0) /* 1b */
935 #define AOC_EFUSE_RESTORE_RDY_LSB BIT(1) /* 1b */
937 #define DFD_SOC_MTCMOS_ACK_LSB BIT(0) /* 1b */
938 #define DFD_SOC_MTCMOS_REQ_LSB BIT(1) /* 1b */
940 #define SC_UNIVPLL_EN_LSB BIT(0) /* 1b */
941 #define SC_MMPLL_EN_LSB BIT(1) /* 1b */
942 #define SC_RSV_PLL_EN_LSB BIT(2) /* 14b */
943 #define APU_26M_CLK_EN_LSB BIT(16) /* 1b */
944 #define IFR_26M_CLK_EN_LSB BIT(17) /* 1b */
945 #define VLP_26M2ULPOSC_EN_LSB BIT(18) /* 1b */
946 #define SC_RSV_CLK_EN_LSB BIT(20) /* 12b */
948 #define EMI_SLB_MODE_MASK_LSB BIT(0) /* 1b */
949 #define SPM2EMI_SLP_PROT_EN_LSB BIT(1) /* 1b */
950 #define SPM2EMI_SLP_PROT_SRC_LSB BIT(2) /* 1b */
951 #define EMI_DRAMC_MD32_SLEEP_IDLE_LSB BIT(4) /* 2b */
952 #define EMI_SLB_ONLY_MODE_LSB BIT(8) /* 2b */
954 #define SPM_SUSPEND_RESUME_FLAG_LSB BIT(0) /* 1b */
956 #define SPM2PMSR_DRAMC_S0_FLAG_LSB BIT(0) /* 1b */
957 #define SPM2PMSR_SYSTEM_POWER_STATE_LSB BIT(4) /* 8b */
959 #define SPM_CKSYS_RTFF_DIVIDER_RST_LSB BIT(0) /* 1b */
960 #define SPM_32K_VCORE_CLK_EN_LSB BIT(1) /* 1b */
961 #define SPM_ULPOSC_VCORE_CLK_EN_LSB BIT(2) /* 1b */
963 #define SPM2EMI_SHF_REQ_LSB BIT(0) /* 2b */
964 #define SPM2EMI_SHF_REQ_ACK_LSB BIT(4) /* 2b */
966 #define SPM_CIRQ_BYPASS_MODE_EN_LSB BIT(0) /* 1b */
968 #define AOC_VCORE_SRAM_PDN_EN_LSB BIT(0) /* 1b */
969 #define AOC_VCORE_SRAM_PDN_SHIFT_LSB BIT(1) /* 1b */
971 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_0_LSB BIT(0) /* 32b */
973 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_1_LSB BIT(0) /* 32b */
975 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_2_LSB BIT(0) /* 32b */
977 #define REG_MODULE_SW_CG_DDREN_REQ_MASK_3_LSB BIT(0) /* 32b */
979 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_0_LSB BIT(0) /* 32b */
981 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_1_LSB BIT(0) /* 32b */
983 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_2_LSB BIT(0) /* 32b */
985 #define REG_MODULE_SW_CG_VRF18_REQ_MASK_3_LSB BIT(0) /* 32b */
987 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_0_LSB BIT(0) /* 32b */
989 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_1_LSB BIT(0) /* 32b */
991 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_2_LSB BIT(0) /* 32b */
993 #define REG_MODULE_SW_CG_INFRA_REQ_MASK_3_LSB BIT(0) /* 32b */
995 #define REG_MODULE_SW_CG_F26M_REQ_MASK_0_LSB BIT(0) /* 32b */
997 #define REG_MODULE_SW_CG_F26M_REQ_MASK_1_LSB BIT(0) /* 32b */
999 #define REG_MODULE_SW_CG_F26M_REQ_MASK_2_LSB BIT(0) /* 32b */
1001 #define REG_MODULE_SW_CG_F26M_REQ_MASK_3_LSB BIT(0) /* 32b */
1003 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_0_LSB BIT(0) /* 32b */
1005 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_1_LSB BIT(0) /* 32b */
1007 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_2_LSB BIT(0) /* 32b */
1009 #define REG_MODULE_SW_CG_VCORE_REQ_MASK_3_LSB BIT(0) /* 32b */
1011 #define REG_PWR_STATUS_DDREN_REQ_MASK_LSB BIT(0) /* 32b */
1013 #define REG_PWR_STATUS_VRF18_REQ_MASK_LSB BIT(0) /* 32b */
1015 #define REG_PWR_STATUS_INFRA_REQ_MASK_LSB BIT(0) /* 32b */
1017 #define REG_PWR_STATUS_F26M_REQ_MASK_LSB BIT(0) /* 32b */
1019 #define REG_PWR_STATUS_PMIC_REQ_MASK_LSB BIT(0) /* 32b */
1021 #define REG_PWR_STATUS_VCORE_REQ_MASK_LSB BIT(0) /* 32b */
1023 #define REG_PWR_STATUS_MSB_DDREN_REQ_MASK_LSB BIT(0) /* 32b */
1025 #define REG_PWR_STATUS_MSB_VRF18_REQ_MASK_LSB BIT(0) /* 32b */
1027 #define REG_PWR_STATUS_MSB_INFRA_REQ_MASK_LSB BIT(0) /* 32b */
1029 #define REG_PWR_STATUS_MSB_F26M_REQ_MASK_LSB BIT(0) /* 32b */
1031 #define REG_PWR_STATUS_MSB_PMIC_REQ_MASK_LSB BIT(0) /* 32b */
1033 #define REG_PWR_STATUS_MSB_VCORE_REQ_MASK_LSB BIT(0) /* 32b */
1035 #define REG_MODULE_BUSY_DDREN_REQ_MASK_LSB BIT(0) /* 32b */
1037 #define REG_MODULE_BUSY_VRF18_REQ_MASK_LSB BIT(0) /* 32b */
1039 #define REG_MODULE_BUSY_INFRA_REQ_MASK_LSB BIT(0) /* 32b */
1041 #define REG_MODULE_BUSY_F26M_REQ_MASK_LSB BIT(0) /* 32b */
1043 #define REG_MODULE_BUSY_PMIC_REQ_MASK_LSB BIT(0) /* 32b */
1045 #define REG_MODULE_BUSY_VCORE_REQ_MASK_LSB BIT(0) /* 32b */
1047 #define SYS_TIMER_START_EN_LSB BIT(0) /* 1b */
1048 #define SYS_TIMER_LATCH_EN_LSB BIT(1) /* 1b */
1049 #define SYS_TIMER_ID_LSB BIT(8) /* 8b */
1050 #define SYS_TIMER_VALID_LSB BIT(31) /* 1b */
1052 #define SYS_TIMER_VALUE_L_LSB BIT(0) /* 32b */
1054 #define SYS_TIMER_VALUE_H_LSB BIT(0) /* 32b */
1056 #define SYS_TIMER_START_L_LSB BIT(0) /* 32b */
1058 #define SYS_TIMER_START_H_LSB BIT(0) /* 32b */
1060 #define SYS_TIMER_LATCH_L_00_LSB BIT(0) /* 32b */
1062 #define SYS_TIMER_LATCH_H_00_LSB BIT(0) /* 32b */
1064 #define SYS_TIMER_LATCH_L_01_LSB BIT(0) /* 32b */
1066 #define SYS_TIMER_LATCH_H_01_LSB BIT(0) /* 32b */
1068 #define SYS_TIMER_LATCH_L_02_LSB BIT(0) /* 32b */
1070 #define SYS_TIMER_LATCH_H_02_LSB BIT(0) /* 32b */
1072 #define SYS_TIMER_LATCH_L_03_LSB BIT(0) /* 32b */
1074 #define SYS_TIMER_LATCH_H_03_LSB BIT(0) /* 32b */
1076 #define SYS_TIMER_LATCH_L_04_LSB BIT(0) /* 32b */
1078 #define SYS_TIMER_LATCH_H_04_LSB BIT(0) /* 32b */
1080 #define SYS_TIMER_LATCH_L_05_LSB BIT(0) /* 32b */
1082 #define SYS_TIMER_LATCH_H_05_LSB BIT(0) /* 32b */
1084 #define SYS_TIMER_LATCH_L_06_LSB BIT(0) /* 32b */
1086 #define SYS_TIMER_LATCH_H_06_LSB BIT(0) /* 32b */
1088 #define SYS_TIMER_LATCH_L_07_LSB BIT(0) /* 32b */
1090 #define SYS_TIMER_LATCH_H_07_LSB BIT(0) /* 32b */
1092 #define SYS_TIMER_LATCH_L_08_LSB BIT(0) /* 32b */
1094 #define SYS_TIMER_LATCH_H_08_LSB BIT(0) /* 32b */
1096 #define SYS_TIMER_LATCH_L_09_LSB BIT(0) /* 32b */
1098 #define SYS_TIMER_LATCH_H_09_LSB BIT(0) /* 32b */
1100 #define SYS_TIMER_LATCH_L_10_LSB BIT(0) /* 32b */
1102 #define SYS_TIMER_LATCH_H_10_LSB BIT(0) /* 32b */
1104 #define SYS_TIMER_LATCH_L_11_LSB BIT(0) /* 32b */
1106 #define SYS_TIMER_LATCH_H_11_LSB BIT(0) /* 32b */
1108 #define SYS_TIMER_LATCH_L_12_LSB BIT(0) /* 32b */
1110 #define SYS_TIMER_LATCH_H_12_LSB BIT(0) /* 32b */
1112 #define SYS_TIMER_LATCH_L_13_LSB BIT(0) /* 32b */
1114 #define SYS_TIMER_LATCH_H_13_LSB BIT(0) /* 32b */
1116 #define SYS_TIMER_LATCH_L_14_LSB BIT(0) /* 32b */
1118 #define SYS_TIMER_LATCH_H_14_LSB BIT(0) /* 32b */
1120 #define SYS_TIMER_LATCH_L_15_LSB BIT(0) /* 32b */
1122 #define SYS_TIMER_LATCH_H_15_LSB BIT(0) /* 32b */
1124 #define REG_PCM_TIMER_VAL_LSB BIT(0) /* 32b */
1126 #define PCM_TIMER_LSB BIT(0) /* 32b */
1128 #define SPM_COUNTER_VAL_0_LSB BIT(0) /* 14b */
1129 #define SPM_COUNTER_OUT_0_LSB BIT(14) /* 14b */
1130 #define SPM_COUNTER_EN_0_LSB BIT(28) /* 1b */
1131 #define SPM_COUNTER_CLR_0_LSB BIT(29) /* 1b */
1132 #define SPM_COUNTER_TIMEOUT_0_LSB BIT(30) /* 1b */
1133 #define SPM_COUNTER_WAKEUP_EN_0_LSB BIT(31) /* 1b */
1135 #define SPM_COUNTER_VAL_1_LSB BIT(0) /* 14b */
1136 #define SPM_COUNTER_OUT_1_LSB BIT(14) /* 14b */
1137 #define SPM_COUNTER_EN_1_LSB BIT(28) /* 1b */
1138 #define SPM_COUNTER_CLR_1_LSB BIT(29) /* 1b */
1139 #define SPM_COUNTER_TIMEOUT_1_LSB BIT(30) /* 1b */
1140 #define SPM_COUNTER_WAKEUP_EN_1_LSB BIT(31) /* 1b */
1142 #define SPM_COUNTER_VAL_2_LSB BIT(0) /* 14b */
1143 #define SPM_COUNTER_OUT_2_LSB BIT(14) /* 14b */
1144 #define SPM_COUNTER_EN_2_LSB BIT(28) /* 1b */
1145 #define SPM_COUNTER_CLR_2_LSB BIT(29) /* 1b */
1146 #define SPM_COUNTER_TIMEOUT_2_LSB BIT(30) /* 1b */
1147 #define SPM_COUNTER_WAKEUP_EN_2_LSB BIT(31) /* 1b */
1149 #define REG_PCM_WDT_VAL_LSB BIT(0) /* 32b */
1151 #define PCM_WDT_TIMER_VAL_OUT_LSB BIT(0) /* 32b */
1153 #define SPM_SW_FLAG_LSB BIT(0) /* 32b */
1155 #define SPM_SW_DEBUG_0_LSB BIT(0) /* 32b */
1157 #define SPM_SW_FLAG_1_LSB BIT(0) /* 32b */
1159 #define SPM_SW_DEBUG_1_LSB BIT(0) /* 32b */
1161 #define SPM_SW_RSV_0_LSB BIT(0) /* 32b */
1163 #define SPM_SW_RSV_1_LSB BIT(0) /* 32b */
1165 #define SPM_SW_RSV_2_LSB BIT(0) /* 32b */
1167 #define SPM_SW_RSV_3_LSB BIT(0) /* 32b */
1169 #define SPM_SW_RSV_4_LSB BIT(0) /* 32b */
1171 #define SPM_SW_RSV_5_LSB BIT(0) /* 32b */
1173 #define SPM_SW_RSV_6_LSB BIT(0) /* 32b */
1175 #define SPM_SW_RSV_7_LSB BIT(0) /* 32b */
1177 #define SPM_SW_RSV_8_LSB BIT(0) /* 32b */
1179 #define SPM_BK_WAKE_EVENT_LSB BIT(0) /* 32b */
1181 #define SPM_BK_VTCXO_DUR_LSB BIT(0) /* 32b */
1183 #define SPM_BK_WAKE_MISC_LSB BIT(0) /* 32b */
1185 #define SPM_BK_PCM_TIMER_LSB BIT(0) /* 32b */
1187 #define SPM_RSV_CON_0_LSB BIT(0) /* 32b */
1189 #define SPM_RSV_CON_1_LSB BIT(0) /* 32b */
1191 #define SPM_RSV_STA_0_LSB BIT(0) /* 32b */
1193 #define SPM_RSV_STA_1_LSB BIT(0) /* 32b */
1195 #define SPM_SPARE_CON_LSB BIT(0) /* 32b */
1197 #define SPM_SPARE_CON_SET_LSB BIT(0) /* 32b */
1199 #define SPM_SPARE_CON_CLR_LSB BIT(0) /* 32b */
1201 #define SPM_M0_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */
1202 #define SPM_CROSS_WAKE_M0_CHK_LSB BIT(4) /* 4b */
1204 #define SPM_M1_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */
1205 #define SPM_CROSS_WAKE_M1_CHK_LSB BIT(4) /* 4b */
1207 #define SPM_M2_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */
1208 #define SPM_CROSS_WAKE_M2_CHK_LSB BIT(4) /* 4b */
1210 #define SPM_M3_CROSS_WAKE_REQ_LSB BIT(0) /* 4b */
1211 #define SPM_CROSS_WAKE_M3_CHK_LSB BIT(4) /* 4b */
1213 #define SCP_VCORE_LEVEL_LSB BIT(0) /* 16b */
1215 #define SPM_DDREN_ACK_SEL_OTHERS_LSB BIT(0) /* 1b */
1216 #define SPM_DDREN_ACK_SEL_MCU_LSB BIT(1) /* 1b */
1218 #define SPM_SW_FLAG_2_LSB BIT(0) /* 32b */
1220 #define SPM_SW_DEBUG_2_LSB BIT(0) /* 32b */
1222 #define SPM_DV_CON_0_LSB BIT(0) /* 32b */
1224 #define SPM_DV_CON_1_LSB BIT(0) /* 32b */
1226 #define SPM_SEMA_M0_LSB BIT(0) /* 8b */
1228 #define SPM_SEMA_M1_LSB BIT(0) /* 8b */
1230 #define SPM_SEMA_M2_LSB BIT(0) /* 8b */
1232 #define SPM_SEMA_M3_LSB BIT(0) /* 8b */
1234 #define SPM_SEMA_M4_LSB BIT(0) /* 8b */
1236 #define SPM_SEMA_M5_LSB BIT(0) /* 8b */
1238 #define SPM_SEMA_M6_LSB BIT(0) /* 8b */
1240 #define SPM_SEMA_M7_LSB BIT(0) /* 8b */
1242 #define SPM2ADSP_MAILBOX_LSB BIT(0) /* 32b */
1244 #define ADSP2SPM_MAILBOX_LSB BIT(0) /* 32b */
1246 #define VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */
1248 #define VCORE_RTFF_CTRL_MASK_CLR_VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */
1250 #define SPM2PMCU_MAILBOX_0_LSB BIT(0) /* 32b */
1252 #define SPM2PMCU_MAILBOX_1_LSB BIT(0) /* 32b */
1254 #define SPM2PMCU_MAILBOX_2_LSB BIT(0) /* 32b */
1256 #define SPM2PMCU_MAILBOX_3_LSB BIT(0) /* 32b */
1258 #define PMCU2SPM_MAILBOX_0_LSB BIT(0) /* 32b */
1260 #define PMCU2SPM_MAILBOX_1_LSB BIT(0) /* 32b */
1262 #define PMCU2SPM_MAILBOX_2_LSB BIT(0) /* 32b */
1264 #define PMCU2SPM_MAILBOX_3_LSB BIT(0) /* 32b */
1266 #define SPM_SCP_MAILBOX_LSB BIT(0) /* 32b */
1268 #define SCP_SPM_MAILBOX_LSB BIT(0) /* 32b */
1270 #define SCP_AOV_BUS_REQ_LSB BIT(0) /* 1b */
1271 #define SCP_AOV_BUS_ACK_LSB BIT(8) /* 1b */
1273 #define VCORE_RTFF_CTRL_MASK_VCORE_RTFF_CTRL_MASK_LSB BIT(0) /* 32b */
1275 #define SPM_SRAM_SRCLKENO_MASK_LSB BIT(0) /* 1b */
1277 #define EMI_PDN_REQ_LSB BIT(0) /* 32b */
1279 #define EMI_BUSY_REQ_LSB BIT(0) /* 32b */
1281 #define EMI_RESERVED_STA_LSB BIT(0) /* 32b */
1283 #define SC_UNIVPLL_DIV_RST_B_LSB BIT(0) /* 32b */
1285 #define ECO_ARMPLL_DIV_CLOCK_OFF_LSB BIT(0) /* 32b */
1287 #define SPM_MCDSR_CG_CHECK_X1_LSB BIT(0) /* 32b */
1289 #define SPM_SODI2_CG_CHECK_X1_LSB BIT(0) /* 32b */
1291 #define SPM_WAKEUP_EVENT_L_LSB BIT(0) /* 32b */
1293 #define EXT_WAKEUP_EVENT_LSB BIT(0) /* 32b */
1295 #define REG_WAKEUP_EVENT_MASK_LSB BIT(0) /* 32b */
1297 #define REG_EXT_WAKEUP_EVENT_MASK_LSB BIT(0) /* 32b */
1299 #define REG_WAKEUP_EVENT_SENS_LSB BIT(0) /* 32b */
1301 #define REG_WAKEUP_EVENT_CLR_LSB BIT(0) /* 32b */
1303 #define REG_SPM_ADSP_MAILBOX_REQ_LSB BIT(0) /* 1b */
1304 #define REG_SPM_APSRC_REQ_LSB BIT(1) /* 1b */
1305 #define REG_SPM_DDREN_REQ_LSB BIT(2) /* 1b */
1306 #define REG_SPM_DVFS_REQ_LSB BIT(3) /* 1b */
1307 #define REG_SPM_EMI_REQ_LSB BIT(4) /* 1b */
1308 #define REG_SPM_F26M_REQ_LSB BIT(5) /* 1b */
1309 #define REG_SPM_INFRA_REQ_LSB BIT(6) /* 1b */
1310 #define REG_SPM_PMIC_REQ_LSB BIT(7) /* 1b */
1311 #define REG_SPM_SCP_MAILBOX_REQ_LSB BIT(8) /* 1b */
1312 #define REG_SPM_SSPM_MAILBOX_REQ_LSB BIT(9) /* 1b */
1313 #define REG_SPM_SW_MAILBOX_REQ_LSB BIT(10) /* 1b */
1314 #define REG_SPM_VCORE_REQ_LSB BIT(11) /* 1b */
1315 #define REG_SPM_VRF18_REQ_LSB BIT(12) /* 1b */
1316 #define ADSP_MAILBOX_STATE_LSB BIT(16) /* 1b */
1317 #define APSRC_STATE_LSB BIT(17) /* 1b */
1318 #define DDREN_STATE_LSB BIT(18) /* 1b */
1319 #define DVFS_STATE_LSB BIT(19) /* 1b */
1320 #define EMI_STATE_LSB BIT(20) /* 1b */
1321 #define F26M_STATE_LSB BIT(21) /* 1b */
1322 #define INFRA_STATE_LSB BIT(22) /* 1b */
1323 #define PMIC_STATE_LSB BIT(23) /* 1b */
1324 #define SCP_MAILBOX_STATE_LSB BIT(24) /* 1b */
1325 #define SSPM_MAILBOX_STATE_LSB BIT(25) /* 1b */
1326 #define SW_MAILBOX_STATE_LSB BIT(26) /* 1b */
1327 #define VCORE_STATE_LSB BIT(27) /* 1b */
1328 #define VRF18_STATE_LSB BIT(28) /* 1b */
1330 #define REG_APU_APSRC_REQ_MASK_B_LSB BIT(0) /* 1b */
1331 #define REG_APU_DDREN_REQ_MASK_B_LSB BIT(1) /* 1b */
1332 #define REG_APU_EMI_REQ_MASK_B_LSB BIT(2) /* 1b */
1333 #define REG_APU_INFRA_REQ_MASK_B_LSB BIT(3) /* 1b */
1334 #define REG_APU_PMIC_REQ_MASK_B_LSB BIT(4) /* 1b */
1335 #define REG_APU_SRCCLKENA_MASK_B_LSB BIT(5) /* 1b */
1336 #define REG_APU_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */
1337 #define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB BIT(7) /* 1b */
1338 #define REG_AUDIO_DSP_DDREN_REQ_MASK_B_LSB BIT(8) /* 1b */
1339 #define REG_AUDIO_DSP_EMI_REQ_MASK_B_LSB BIT(9) /* 1b */
1340 #define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB BIT(10) /* 1b */
1341 #define REG_AUDIO_DSP_PMIC_REQ_MASK_B_LSB BIT(11) /* 1b */
1342 #define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB BIT(12) /* 1b */
1343 #define REG_AUDIO_DSP_VCORE_REQ_MASK_B_LSB BIT(13) /* 1b */
1344 #define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB BIT(14) /* 1b */
1345 #define REG_CAM_APSRC_REQ_MASK_B_LSB BIT(15) /* 1b */
1346 #define REG_CAM_DDREN_REQ_MASK_B_LSB BIT(16) /* 1b */
1347 #define REG_CAM_EMI_REQ_MASK_B_LSB BIT(17) /* 1b */
1348 #define REG_CAM_INFRA_REQ_MASK_B_LSB BIT(18) /* 1b */
1349 #define REG_CAM_PMIC_REQ_MASK_B_LSB BIT(19) /* 1b */
1350 #define REG_CAM_SRCCLKENA_MASK_B_LSB BIT(20) /* 1b */
1351 #define REG_CAM_VRF18_REQ_MASK_B_LSB BIT(21) /* 1b */
1353 #define REG_CCIF_APSRC_REQ_MASK_B_LSB BIT(0) /* 12b */
1354 #define REG_CCIF_EMI_REQ_MASK_B_LSB BIT(12) /* 12b */
1356 #define REG_CCIF_INFRA_REQ_MASK_B_LSB BIT(0) /* 12b */
1357 #define REG_CCIF_PMIC_REQ_MASK_B_LSB BIT(12) /* 12b */
1359 #define REG_CCIF_SRCCLKENA_MASK_B_LSB BIT(0) /* 12b */
1360 #define REG_CCIF_VRF18_REQ_MASK_B_LSB BIT(12) /* 12b */
1361 #define REG_CCU_APSRC_REQ_MASK_B_LSB BIT(24) /* 1b */
1362 #define REG_CCU_DDREN_REQ_MASK_B_LSB BIT(25) /* 1b */
1363 #define REG_CCU_EMI_REQ_MASK_B_LSB BIT(26) /* 1b */
1364 #define REG_CCU_INFRA_REQ_MASK_B_LSB BIT(27) /* 1b */
1365 #define REG_CCU_PMIC_REQ_MASK_B_LSB BIT(28) /* 1b */
1366 #define REG_CCU_SRCCLKENA_MASK_B_LSB BIT(29) /* 1b */
1367 #define REG_CCU_VRF18_REQ_MASK_B_LSB BIT(30) /* 1b */
1368 #define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB BIT(31) /* 1b */
1370 #define REG_CG_CHECK_DDREN_REQ_MASK_B_LSB BIT(0) /* 1b */
1371 #define REG_CG_CHECK_EMI_REQ_MASK_B_LSB BIT(1) /* 1b */
1372 #define REG_CG_CHECK_INFRA_REQ_MASK_B_LSB BIT(2) /* 1b */
1373 #define REG_CG_CHECK_PMIC_REQ_MASK_B_LSB BIT(3) /* 1b */
1374 #define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB BIT(4) /* 1b */
1375 #define REG_CG_CHECK_VCORE_REQ_MASK_B_LSB BIT(5) /* 1b */
1376 #define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */
1377 #define REG_CONN_APSRC_REQ_MASK_B_LSB BIT(7) /* 1b */
1378 #define REG_CONN_DDREN_REQ_MASK_B_LSB BIT(8) /* 1b */
1379 #define REG_CONN_EMI_REQ_MASK_B_LSB BIT(9) /* 1b */
1380 #define REG_CONN_INFRA_REQ_MASK_B_LSB BIT(10) /* 1b */
1381 #define REG_CONN_PMIC_REQ_MASK_B_LSB BIT(11) /* 1b */
1382 #define REG_CONN_SRCCLKENA_MASK_B_LSB BIT(12) /* 1b */
1383 #define REG_CONN_SRCCLKENB_MASK_B_LSB BIT(13) /* 1b */
1384 #define REG_CONN_VCORE_REQ_MASK_B_LSB BIT(14) /* 1b */
1385 #define REG_CONN_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */
1386 #define REG_CPUEB_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */
1387 #define REG_CPUEB_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */
1388 #define REG_CPUEB_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */
1389 #define REG_CPUEB_INFRA_REQ_MASK_B_LSB BIT(19) /* 1b */
1390 #define REG_CPUEB_PMIC_REQ_MASK_B_LSB BIT(20) /* 1b */
1391 #define REG_CPUEB_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */
1392 #define REG_CPUEB_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */
1393 #define REG_DISP0_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */
1394 #define REG_DISP0_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */
1395 #define REG_DISP0_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */
1396 #define REG_DISP0_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */
1397 #define REG_DISP0_PMIC_REQ_MASK_B_LSB BIT(27) /* 1b */
1398 #define REG_DISP0_SRCCLKENA_MASK_B_LSB BIT(28) /* 1b */
1399 #define REG_DISP0_VRF18_REQ_MASK_B_LSB BIT(29) /* 1b */
1400 #define REG_DISP1_APSRC_REQ_MASK_B_LSB BIT(30) /* 1b */
1401 #define REG_DISP1_DDREN_REQ_MASK_B_LSB BIT(31) /* 1b */
1403 #define REG_DISP1_EMI_REQ_MASK_B_LSB BIT(0) /* 1b */
1404 #define REG_DISP1_INFRA_REQ_MASK_B_LSB BIT(1) /* 1b */
1405 #define REG_DISP1_PMIC_REQ_MASK_B_LSB BIT(2) /* 1b */
1406 #define REG_DISP1_SRCCLKENA_MASK_B_LSB BIT(3) /* 1b */
1407 #define REG_DISP1_VRF18_REQ_MASK_B_LSB BIT(4) /* 1b */
1408 #define REG_DPM_APSRC_REQ_MASK_B_LSB BIT(5) /* 4b */
1409 #define REG_DPM_DDREN_REQ_MASK_B_LSB BIT(9) /* 4b */
1410 #define REG_DPM_EMI_REQ_MASK_B_LSB BIT(13) /* 4b */
1411 #define REG_DPM_INFRA_REQ_MASK_B_LSB BIT(17) /* 4b */
1412 #define REG_DPM_PMIC_REQ_MASK_B_LSB BIT(21) /* 4b */
1413 #define REG_DPM_SRCCLKENA_MASK_B_LSB BIT(25) /* 4b */
1415 #define REG_DPM_VCORE_REQ_MASK_B_LSB BIT(0) /* 4b */
1416 #define REG_DPM_VRF18_REQ_MASK_B_LSB BIT(4) /* 4b */
1417 #define REG_DPMAIF_APSRC_REQ_MASK_B_LSB BIT(8) /* 1b */
1418 #define REG_DPMAIF_DDREN_REQ_MASK_B_LSB BIT(9) /* 1b */
1419 #define REG_DPMAIF_EMI_REQ_MASK_B_LSB BIT(10) /* 1b */
1420 #define REG_DPMAIF_INFRA_REQ_MASK_B_LSB BIT(11) /* 1b */
1421 #define REG_DPMAIF_PMIC_REQ_MASK_B_LSB BIT(12) /* 1b */
1422 #define REG_DPMAIF_SRCCLKENA_MASK_B_LSB BIT(13) /* 1b */
1423 #define REG_DPMAIF_VRF18_REQ_MASK_B_LSB BIT(14) /* 1b */
1424 #define REG_DVFSRC_LEVEL_REQ_MASK_B_LSB BIT(15) /* 1b */
1425 #define REG_EMISYS_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */
1426 #define REG_EMISYS_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */
1427 #define REG_EMISYS_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */
1428 #define REG_GCE_D_APSRC_REQ_MASK_B_LSB BIT(19) /* 1b */
1429 #define REG_GCE_D_DDREN_REQ_MASK_B_LSB BIT(20) /* 1b */
1430 #define REG_GCE_D_EMI_REQ_MASK_B_LSB BIT(21) /* 1b */
1431 #define REG_GCE_D_INFRA_REQ_MASK_B_LSB BIT(22) /* 1b */
1432 #define REG_GCE_D_PMIC_REQ_MASK_B_LSB BIT(23) /* 1b */
1433 #define REG_GCE_D_SRCCLKENA_MASK_B_LSB BIT(24) /* 1b */
1434 #define REG_GCE_D_VRF18_REQ_MASK_B_LSB BIT(25) /* 1b */
1435 #define REG_GCE_M_APSRC_REQ_MASK_B_LSB BIT(26) /* 1b */
1436 #define REG_GCE_M_DDREN_REQ_MASK_B_LSB BIT(27) /* 1b */
1437 #define REG_GCE_M_EMI_REQ_MASK_B_LSB BIT(28) /* 1b */
1438 #define REG_GCE_M_INFRA_REQ_MASK_B_LSB BIT(29) /* 1b */
1439 #define REG_GCE_M_PMIC_REQ_MASK_B_LSB BIT(30) /* 1b */
1440 #define REG_GCE_M_SRCCLKENA_MASK_B_LSB BIT(31) /* 1b */
1442 #define REG_GCE_M_VRF18_REQ_MASK_B_LSB BIT(0) /* 1b */
1443 #define REG_GPUEB_APSRC_REQ_MASK_B_LSB BIT(1) /* 1b */
1444 #define REG_GPUEB_DDREN_REQ_MASK_B_LSB BIT(2) /* 1b */
1445 #define REG_GPUEB_EMI_REQ_MASK_B_LSB BIT(3) /* 1b */
1446 #define REG_GPUEB_INFRA_REQ_MASK_B_LSB BIT(4) /* 1b */
1447 #define REG_GPUEB_PMIC_REQ_MASK_B_LSB BIT(5) /* 1b */
1448 #define REG_GPUEB_SRCCLKENA_MASK_B_LSB BIT(6) /* 1b */
1449 #define REG_GPUEB_VRF18_REQ_MASK_B_LSB BIT(7) /* 1b */
1450 #define REG_HWCCF_APSRC_REQ_MASK_B_LSB BIT(8) /* 1b */
1451 #define REG_HWCCF_DDREN_REQ_MASK_B_LSB BIT(9) /* 1b */
1452 #define REG_HWCCF_EMI_REQ_MASK_B_LSB BIT(10) /* 1b */
1453 #define REG_HWCCF_INFRA_REQ_MASK_B_LSB BIT(11) /* 1b */
1454 #define REG_HWCCF_PMIC_REQ_MASK_B_LSB BIT(12) /* 1b */
1455 #define REG_HWCCF_SRCCLKENA_MASK_B_LSB BIT(13) /* 1b */
1456 #define REG_HWCCF_VCORE_REQ_MASK_B_LSB BIT(14) /* 1b */
1457 #define REG_HWCCF_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */
1458 #define REG_IMG_APSRC_REQ_MASK_B_LSB BIT(16) /* 1b */
1459 #define REG_IMG_DDREN_REQ_MASK_B_LSB BIT(17) /* 1b */
1460 #define REG_IMG_EMI_REQ_MASK_B_LSB BIT(18) /* 1b */
1461 #define REG_IMG_INFRA_REQ_MASK_B_LSB BIT(19) /* 1b */
1462 #define REG_IMG_PMIC_REQ_MASK_B_LSB BIT(20) /* 1b */
1463 #define REG_IMG_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */
1464 #define REG_IMG_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */
1465 #define REG_INFRASYS_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */
1466 #define REG_INFRASYS_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */
1467 #define REG_INFRASYS_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */
1468 #define REG_IPIC_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */
1469 #define REG_IPIC_VRF18_REQ_MASK_B_LSB BIT(27) /* 1b */
1470 #define REG_MCU_APSRC_REQ_MASK_B_LSB BIT(28) /* 1b */
1471 #define REG_MCU_DDREN_REQ_MASK_B_LSB BIT(29) /* 1b */
1472 #define REG_MCU_EMI_REQ_MASK_B_LSB BIT(30) /* 1b */
1474 #define REG_MCUSYS_APSRC_REQ_MASK_B_LSB BIT(0) /* 8b */
1475 #define REG_MCUSYS_DDREN_REQ_MASK_B_LSB BIT(8) /* 8b */
1476 #define REG_MCUSYS_EMI_REQ_MASK_B_LSB BIT(16) /* 8b */
1477 #define REG_MCUSYS_INFRA_REQ_MASK_B_LSB BIT(24) /* 8b */
1479 #define REG_MCUSYS_PMIC_REQ_MASK_B_LSB BIT(0) /* 8b */
1480 #define REG_MCUSYS_SRCCLKENA_MASK_B_LSB BIT(8) /* 8b */
1481 #define REG_MCUSYS_VRF18_REQ_MASK_B_LSB BIT(16) /* 8b */
1482 #define REG_MD_APSRC_REQ_MASK_B_LSB BIT(24) /* 1b */
1483 #define REG_MD_DDREN_REQ_MASK_B_LSB BIT(25) /* 1b */
1484 #define REG_MD_EMI_REQ_MASK_B_LSB BIT(26) /* 1b */
1485 #define REG_MD_INFRA_REQ_MASK_B_LSB BIT(27) /* 1b */
1486 #define REG_MD_PMIC_REQ_MASK_B_LSB BIT(28) /* 1b */
1487 #define REG_MD_SRCCLKENA_MASK_B_LSB BIT(29) /* 1b */
1488 #define REG_MD_SRCCLKENA1_MASK_B_LSB BIT(30) /* 1b */
1489 #define REG_MD_VCORE_REQ_MASK_B_LSB BIT(31) /* 1b */
1491 #define REG_MD_VRF18_REQ_MASK_B_LSB BIT(0) /* 1b */
1492 #define REG_MDP_APSRC_REQ_MASK_B_LSB BIT(1) /* 1b */
1493 #define REG_MDP_DDREN_REQ_MASK_B_LSB BIT(2) /* 1b */
1494 #define REG_MM_PROC_APSRC_REQ_MASK_B_LSB BIT(3) /* 1b */
1495 #define REG_MM_PROC_DDREN_REQ_MASK_B_LSB BIT(4) /* 1b */
1496 #define REG_MM_PROC_EMI_REQ_MASK_B_LSB BIT(5) /* 1b */
1497 #define REG_MM_PROC_INFRA_REQ_MASK_B_LSB BIT(6) /* 1b */
1498 #define REG_MM_PROC_PMIC_REQ_MASK_B_LSB BIT(7) /* 1b */
1499 #define REG_MM_PROC_SRCCLKENA_MASK_B_LSB BIT(8) /* 1b */
1500 #define REG_MM_PROC_VRF18_REQ_MASK_B_LSB BIT(9) /* 1b */
1501 #define REG_MMSYS_APSRC_REQ_MASK_B_LSB BIT(10) /* 1b */
1502 #define REG_MMSYS_DDREN_REQ_MASK_B_LSB BIT(11) /* 1b */
1503 #define REG_MMSYS_VRF18_REQ_MASK_B_LSB BIT(12) /* 1b */
1504 #define REG_PCIE0_APSRC_REQ_MASK_B_LSB BIT(13) /* 1b */
1505 #define REG_PCIE0_DDREN_REQ_MASK_B_LSB BIT(14) /* 1b */
1506 #define REG_PCIE0_INFRA_REQ_MASK_B_LSB BIT(15) /* 1b */
1507 #define REG_PCIE0_SRCCLKENA_MASK_B_LSB BIT(16) /* 1b */
1508 #define REG_PCIE0_VRF18_REQ_MASK_B_LSB BIT(17) /* 1b */
1509 #define REG_PCIE1_APSRC_REQ_MASK_B_LSB BIT(18) /* 1b */
1510 #define REG_PCIE1_DDREN_REQ_MASK_B_LSB BIT(19) /* 1b */
1511 #define REG_PCIE1_INFRA_REQ_MASK_B_LSB BIT(20) /* 1b */
1512 #define REG_PCIE1_SRCCLKENA_MASK_B_LSB BIT(21) /* 1b */
1513 #define REG_PCIE1_VRF18_REQ_MASK_B_LSB BIT(22) /* 1b */
1514 #define REG_PERISYS_APSRC_REQ_MASK_B_LSB BIT(23) /* 1b */
1515 #define REG_PERISYS_DDREN_REQ_MASK_B_LSB BIT(24) /* 1b */
1516 #define REG_PERISYS_EMI_REQ_MASK_B_LSB BIT(25) /* 1b */
1517 #define REG_PERISYS_INFRA_REQ_MASK_B_LSB BIT(26) /* 1b */
1518 #define REG_PERISYS_PMIC_REQ_MASK_B_LSB BIT(27) /* 1b */
1519 #define REG_PERISYS_SRCCLKENA_MASK_B_LSB BIT(28) /* 1b */
1520 #define REG_PERISYS_VCORE_REQ_MASK_B_LSB BIT(29) /* 1b */
1521 #define REG_PERISYS_VRF18_REQ_MASK_B_LSB BIT(30) /* 1b */
1522 #define REG_SCP_APSRC_REQ_MASK_B_LSB BIT(31) /* 1b */
1524 #define REG_SCP_DDREN_REQ_MASK_B_LSB BIT(0) /* 1b */
1525 #define REG_SCP_EMI_REQ_MASK_B_LSB BIT(1) /* 1b */
1526 #define REG_SCP_INFRA_REQ_MASK_B_LSB BIT(2) /* 1b */
1527 #define REG_SCP_PMIC_REQ_MASK_B_LSB BIT(3) /* 1b */
1528 #define REG_SCP_SRCCLKENA_MASK_B_LSB BIT(4) /* 1b */
1529 #define REG_SCP_VCORE_REQ_MASK_B_LSB BIT(5) /* 1b */
1530 #define REG_SCP_VRF18_REQ_MASK_B_LSB BIT(6) /* 1b */
1531 #define REG_SRCCLKENI_INFRA_REQ_MASK_B_LSB BIT(7) /* 2b */
1532 #define REG_SRCCLKENI_PMIC_REQ_MASK_B_LSB BIT(9) /* 2b */
1533 #define REG_SRCCLKENI_SRCCLKENA_MASK_B_LSB BIT(11) /* 2b */
1534 #define REG_SSPM_APSRC_REQ_MASK_B_LSB BIT(13) /* 1b */
1535 #define REG_SSPM_DDREN_REQ_MASK_B_LSB BIT(14) /* 1b */
1536 #define REG_SSPM_EMI_REQ_MASK_B_LSB BIT(15) /* 1b */
1537 #define REG_SSPM_INFRA_REQ_MASK_B_LSB BIT(16) /* 1b */
1538 #define REG_SSPM_PMIC_REQ_MASK_B_LSB BIT(17) /* 1b */
1539 #define REG_SSPM_SRCCLKENA_MASK_B_LSB BIT(18) /* 1b */
1540 #define REG_SSPM_VRF18_REQ_MASK_B_LSB BIT(19) /* 1b */
1541 #define REG_SSR_APSRC_REQ_MASK_B_LSB BIT(20) /* 1b */
1542 #define REG_SSR_DDREN_REQ_MASK_B_LSB BIT(21) /* 1b */
1543 #define REG_SSR_EMI_REQ_MASK_B_LSB BIT(22) /* 1b */
1544 #define REG_SSR_INFRA_REQ_MASK_B_LSB BIT(23) /* 1b */
1545 #define REG_SSR_PMIC_REQ_MASK_B_LSB BIT(24) /* 1b */
1546 #define REG_SSR_SRCCLKENA_MASK_B_LSB BIT(25) /* 1b */
1547 #define REG_SSR_VRF18_REQ_MASK_B_LSB BIT(26) /* 1b */
1548 #define REG_UFS_APSRC_REQ_MASK_B_LSB BIT(27) /* 1b */
1549 #define REG_UFS_DDREN_REQ_MASK_B_LSB BIT(28) /* 1b */
1550 #define REG_UFS_EMI_REQ_MASK_B_LSB BIT(29) /* 1b */
1551 #define REG_UFS_INFRA_REQ_MASK_B_LSB BIT(30) /* 1b */
1552 #define REG_UFS_PMIC_REQ_MASK_B_LSB BIT(31) /* 1b */
1554 #define REG_UFS_SRCCLKENA_MASK_B_LSB BIT(0) /* 1b */
1555 #define REG_UFS_VRF18_REQ_MASK_B_LSB BIT(1) /* 1b */
1556 #define REG_VDEC_APSRC_REQ_MASK_B_LSB BIT(2) /* 1b */
1557 #define REG_VDEC_DDREN_REQ_MASK_B_LSB BIT(3) /* 1b */
1558 #define REG_VDEC_EMI_REQ_MASK_B_LSB BIT(4) /* 1b */
1559 #define REG_VDEC_INFRA_REQ_MASK_B_LSB BIT(5) /* 1b */
1560 #define REG_VDEC_PMIC_REQ_MASK_B_LSB BIT(6) /* 1b */
1561 #define REG_VDEC_SRCCLKENA_MASK_B_LSB BIT(7) /* 1b */
1562 #define REG_VDEC_VRF18_REQ_MASK_B_LSB BIT(8) /* 1b */
1563 #define REG_VENC_APSRC_REQ_MASK_B_LSB BIT(9) /* 1b */
1564 #define REG_VENC_DDREN_REQ_MASK_B_LSB BIT(10) /* 1b */
1565 #define REG_VENC_EMI_REQ_MASK_B_LSB BIT(11) /* 1b */
1566 #define REG_VENC_INFRA_REQ_MASK_B_LSB BIT(12) /* 1b */
1567 #define REG_VENC_PMIC_REQ_MASK_B_LSB BIT(13) /* 1b */
1568 #define REG_VENC_SRCCLKENA_MASK_B_LSB BIT(14) /* 1b */
1569 #define REG_VENC_VRF18_REQ_MASK_B_LSB BIT(15) /* 1b */
1571 #define APU_APSRC_REQ_LSB BIT(0) /* 1b */
1572 #define APU_DDREN_REQ_LSB BIT(1) /* 1b */
1573 #define APU_EMI_REQ_LSB BIT(2) /* 1b */
1574 #define APU_INFRA_REQ_LSB BIT(3) /* 1b */
1575 #define APU_PMIC_REQ_LSB BIT(4) /* 1b */
1576 #define APU_SRCCLKENA_LSB BIT(5) /* 1b */
1577 #define APU_VRF18_REQ_LSB BIT(6) /* 1b */
1578 #define AUDIO_DSP_APSRC_REQ_LSB BIT(7) /* 1b */
1579 #define AUDIO_DSP_DDREN_REQ_LSB BIT(8) /* 1b */
1580 #define AUDIO_DSP_EMI_REQ_LSB BIT(9) /* 1b */
1581 #define AUDIO_DSP_INFRA_REQ_LSB BIT(10) /* 1b */
1582 #define AUDIO_DSP_PMIC_REQ_LSB BIT(11) /* 1b */
1583 #define AUDIO_DSP_SRCCLKENA_LSB BIT(12) /* 1b */
1584 #define AUDIO_DSP_VCORE_REQ_LSB BIT(13) /* 1b */
1585 #define AUDIO_DSP_VRF18_REQ_LSB BIT(14) /* 1b */
1586 #define CAM_APSRC_REQ_LSB BIT(15) /* 1b */
1587 #define CAM_DDREN_REQ_LSB BIT(16) /* 1b */
1588 #define CAM_EMI_REQ_LSB BIT(17) /* 1b */
1589 #define CAM_INFRA_REQ_LSB BIT(18) /* 1b */
1590 #define CAM_PMIC_REQ_LSB BIT(19) /* 1b */
1591 #define CAM_SRCCLKENA_LSB BIT(20) /* 1b */
1592 #define CAM_VRF18_REQ_LSB BIT(21) /* 1b */
1594 #define CCIF_APSRC_REQ_LSB BIT(0) /* 12b */
1595 #define CCIF_EMI_REQ_LSB BIT(12) /* 12b */
1597 #define CCIF_INFRA_REQ_LSB BIT(0) /* 12b */
1598 #define CCIF_PMIC_REQ_LSB BIT(12) /* 12b */
1600 #define CCIF_SRCCLKENA_LSB BIT(0) /* 12b */
1601 #define CCIF_VRF18_REQ_LSB BIT(12) /* 12b */
1602 #define CCU_APSRC_REQ_LSB BIT(24) /* 1b */
1603 #define CCU_DDREN_REQ_LSB BIT(25) /* 1b */
1604 #define CCU_EMI_REQ_LSB BIT(26) /* 1b */
1605 #define CCU_INFRA_REQ_LSB BIT(27) /* 1b */
1606 #define CCU_PMIC_REQ_LSB BIT(28) /* 1b */
1607 #define CCU_SRCCLKENA_LSB BIT(29) /* 1b */
1608 #define CCU_VRF18_REQ_LSB BIT(30) /* 1b */
1609 #define CG_CHECK_APSRC_REQ_LSB BIT(31) /* 1b */
1611 #define CG_CHECK_DDREN_REQ_LSB BIT(0) /* 1b */
1612 #define CG_CHECK_EMI_REQ_LSB BIT(1) /* 1b */
1613 #define CG_CHECK_INFRA_REQ_LSB BIT(2) /* 1b */
1614 #define CG_CHECK_PMIC_REQ_LSB BIT(3) /* 1b */
1615 #define CG_CHECK_SRCCLKENA_LSB BIT(4) /* 1b */
1616 #define CG_CHECK_VCORE_REQ_LSB BIT(5) /* 1b */
1617 #define CG_CHECK_VRF18_REQ_LSB BIT(6) /* 1b */
1618 #define CONN_APSRC_REQ_LSB BIT(7) /* 1b */
1619 #define CONN_DDREN_REQ_LSB BIT(8) /* 1b */
1620 #define CONN_EMI_REQ_LSB BIT(9) /* 1b */
1621 #define CONN_INFRA_REQ_LSB BIT(10) /* 1b */
1622 #define CONN_PMIC_REQ_LSB BIT(11) /* 1b */
1623 #define CONN_SRCCLKENA_LSB BIT(12) /* 1b */
1624 #define CONN_SRCCLKENB_LSB BIT(13) /* 1b */
1625 #define CONN_VCORE_REQ_LSB BIT(14) /* 1b */
1626 #define CONN_VRF18_REQ_LSB BIT(15) /* 1b */
1627 #define CPUEB_APSRC_REQ_LSB BIT(16) /* 1b */
1628 #define CPUEB_DDREN_REQ_LSB BIT(17) /* 1b */
1629 #define CPUEB_EMI_REQ_LSB BIT(18) /* 1b */
1630 #define CPUEB_INFRA_REQ_LSB BIT(19) /* 1b */
1631 #define CPUEB_PMIC_REQ_LSB BIT(20) /* 1b */
1632 #define CPUEB_SRCCLKENA_LSB BIT(21) /* 1b */
1633 #define CPUEB_VRF18_REQ_LSB BIT(22) /* 1b */
1634 #define DISP0_APSRC_REQ_LSB BIT(23) /* 1b */
1635 #define DISP0_DDREN_REQ_LSB BIT(24) /* 1b */
1636 #define DISP0_EMI_REQ_LSB BIT(25) /* 1b */
1637 #define DISP0_INFRA_REQ_LSB BIT(26) /* 1b */
1638 #define DISP0_PMIC_REQ_LSB BIT(27) /* 1b */
1639 #define DISP0_SRCCLKENA_LSB BIT(28) /* 1b */
1640 #define DISP0_VRF18_REQ_LSB BIT(29) /* 1b */
1641 #define DISP1_APSRC_REQ_LSB BIT(30) /* 1b */
1642 #define DISP1_DDREN_REQ_LSB BIT(31) /* 1b */
1644 #define DISP1_EMI_REQ_LSB BIT(0) /* 1b */
1645 #define DISP1_INFRA_REQ_LSB BIT(1) /* 1b */
1646 #define DISP1_PMIC_REQ_LSB BIT(2) /* 1b */
1647 #define DISP1_SRCCLKENA_LSB BIT(3) /* 1b */
1648 #define DISP1_VRF18_REQ_LSB BIT(4) /* 1b */
1649 #define DPM_APSRC_REQ_LSB BIT(5) /* 4b */
1650 #define DPM_DDREN_REQ_LSB BIT(9) /* 4b */
1651 #define DPM_EMI_REQ_LSB BIT(13) /* 4b */
1652 #define DPM_INFRA_REQ_LSB BIT(17) /* 4b */
1653 #define DPM_PMIC_REQ_LSB BIT(21) /* 4b */
1654 #define DPM_SRCCLKENA_LSB BIT(25) /* 4b */
1656 #define DPM_VCORE_REQ_LSB BIT(0) /* 4b */
1657 #define DPM_VRF18_REQ_LSB BIT(4) /* 4b */
1658 #define DPMAIF_APSRC_REQ_LSB BIT(8) /* 1b */
1659 #define DPMAIF_DDREN_REQ_LSB BIT(9) /* 1b */
1660 #define DPMAIF_EMI_REQ_LSB BIT(10) /* 1b */
1661 #define DPMAIF_INFRA_REQ_LSB BIT(11) /* 1b */
1662 #define DPMAIF_PMIC_REQ_LSB BIT(12) /* 1b */
1663 #define DPMAIF_SRCCLKENA_LSB BIT(13) /* 1b */
1664 #define DPMAIF_VRF18_REQ_LSB BIT(14) /* 1b */
1665 #define DVFSRC_LEVEL_REQ_LSB BIT(15) /* 1b */
1666 #define EMISYS_APSRC_REQ_LSB BIT(16) /* 1b */
1667 #define EMISYS_DDREN_REQ_LSB BIT(17) /* 1b */
1668 #define EMISYS_EMI_REQ_LSB BIT(18) /* 1b */
1669 #define GCE_D_APSRC_REQ_LSB BIT(19) /* 1b */
1670 #define GCE_D_DDREN_REQ_LSB BIT(20) /* 1b */
1671 #define GCE_D_EMI_REQ_LSB BIT(21) /* 1b */
1672 #define GCE_D_INFRA_REQ_LSB BIT(22) /* 1b */
1673 #define GCE_D_PMIC_REQ_LSB BIT(23) /* 1b */
1674 #define GCE_D_SRCCLKENA_LSB BIT(24) /* 1b */
1675 #define GCE_D_VRF18_REQ_LSB BIT(25) /* 1b */
1676 #define GCE_M_APSRC_REQ_LSB BIT(26) /* 1b */
1677 #define GCE_M_DDREN_REQ_LSB BIT(27) /* 1b */
1678 #define GCE_M_EMI_REQ_LSB BIT(28) /* 1b */
1679 #define GCE_M_INFRA_REQ_LSB BIT(29) /* 1b */
1680 #define GCE_M_PMIC_REQ_LSB BIT(30) /* 1b */
1681 #define GCE_M_SRCCLKENA_LSB BIT(31) /* 1b */
1683 #define GCE_M_VRF18_REQ_LSB BIT(0) /* 1b */
1684 #define GPUEB_APSRC_REQ_LSB BIT(1) /* 1b */
1685 #define GPUEB_DDREN_REQ_LSB BIT(2) /* 1b */
1686 #define GPUEB_EMI_REQ_LSB BIT(3) /* 1b */
1687 #define GPUEB_INFRA_REQ_LSB BIT(4) /* 1b */
1688 #define GPUEB_PMIC_REQ_LSB BIT(5) /* 1b */
1689 #define GPUEB_SRCCLKENA_LSB BIT(6) /* 1b */
1690 #define GPUEB_VRF18_REQ_LSB BIT(7) /* 1b */
1691 #define HWCCF_APSRC_REQ_LSB BIT(8) /* 1b */
1692 #define HWCCF_DDREN_REQ_LSB BIT(9) /* 1b */
1693 #define HWCCF_EMI_REQ_LSB BIT(10) /* 1b */
1694 #define HWCCF_INFRA_REQ_LSB BIT(11) /* 1b */
1695 #define HWCCF_PMIC_REQ_LSB BIT(12) /* 1b */
1696 #define HWCCF_SRCCLKENA_LSB BIT(13) /* 1b */
1697 #define HWCCF_VCORE_REQ_LSB BIT(14) /* 1b */
1698 #define HWCCF_VRF18_REQ_LSB BIT(15) /* 1b */
1699 #define IMG_APSRC_REQ_LSB BIT(16) /* 1b */
1700 #define IMG_DDREN_REQ_LSB BIT(17) /* 1b */
1701 #define IMG_EMI_REQ_LSB BIT(18) /* 1b */
1702 #define IMG_INFRA_REQ_LSB BIT(19) /* 1b */
1703 #define IMG_PMIC_REQ_LSB BIT(20) /* 1b */
1704 #define IMG_SRCCLKENA_LSB BIT(21) /* 1b */
1705 #define IMG_VRF18_REQ_LSB BIT(22) /* 1b */
1706 #define INFRASYS_APSRC_REQ_LSB BIT(23) /* 1b */
1707 #define INFRASYS_DDREN_REQ_LSB BIT(24) /* 1b */
1708 #define INFRASYS_EMI_REQ_LSB BIT(25) /* 1b */
1709 #define IPIC_INFRA_REQ_LSB BIT(26) /* 1b */
1710 #define IPIC_VRF18_REQ_LSB BIT(27) /* 1b */
1711 #define MCU_APSRC_REQ_LSB BIT(28) /* 1b */
1712 #define MCU_DDREN_REQ_LSB BIT(29) /* 1b */
1713 #define MCU_EMI_REQ_LSB BIT(30) /* 1b */
1715 #define MCUSYS_APSRC_REQ_LSB BIT(0) /* 8b */
1716 #define MCUSYS_DDREN_REQ_LSB BIT(8) /* 8b */
1717 #define MCUSYS_EMI_REQ_LSB BIT(16) /* 8b */
1718 #define MCUSYS_INFRA_REQ_LSB BIT(24) /* 8b */
1720 #define MCUSYS_PMIC_REQ_LSB BIT(0) /* 8b */
1721 #define MCUSYS_SRCCLKENA_LSB BIT(8) /* 8b */
1722 #define MCUSYS_VRF18_REQ_LSB BIT(16) /* 8b */
1723 #define MD_APSRC_REQ_LSB BIT(24) /* 1b */
1724 #define MD_DDREN_REQ_LSB BIT(25) /* 1b */
1725 #define MD_EMI_REQ_LSB BIT(26) /* 1b */
1726 #define MD_INFRA_REQ_LSB BIT(27) /* 1b */
1727 #define MD_PMIC_REQ_LSB BIT(28) /* 1b */
1728 #define MD_SRCCLKENA_LSB BIT(29) /* 1b */
1729 #define MD_SRCCLKENA1_LSB BIT(30) /* 1b */
1730 #define MD_VCORE_REQ_LSB BIT(31) /* 1b */
1732 #define MD_VRF18_REQ_LSB BIT(0) /* 1b */
1733 #define MDP_APSRC_REQ_LSB BIT(1) /* 1b */
1734 #define MDP_DDREN_REQ_LSB BIT(2) /* 1b */
1735 #define MM_PROC_APSRC_REQ_LSB BIT(3) /* 1b */
1736 #define MM_PROC_DDREN_REQ_LSB BIT(4) /* 1b */
1737 #define MM_PROC_EMI_REQ_LSB BIT(5) /* 1b */
1738 #define MM_PROC_INFRA_REQ_LSB BIT(6) /* 1b */
1739 #define MM_PROC_PMIC_REQ_LSB BIT(7) /* 1b */
1740 #define MM_PROC_SRCCLKENA_LSB BIT(8) /* 1b */
1741 #define MM_PROC_VRF18_REQ_LSB BIT(9) /* 1b */
1742 #define MMSYS_APSRC_REQ_LSB BIT(10) /* 1b */
1743 #define MMSYS_DDREN_REQ_LSB BIT(11) /* 1b */
1744 #define MMSYS_VRF18_REQ_LSB BIT(12) /* 1b */
1745 #define PCIE0_APSRC_REQ_LSB BIT(13) /* 1b */
1746 #define PCIE0_DDREN_REQ_LSB BIT(14) /* 1b */
1747 #define PCIE0_INFRA_REQ_LSB BIT(15) /* 1b */
1748 #define PCIE0_SRCCLKENA_LSB BIT(16) /* 1b */
1749 #define PCIE0_VRF18_REQ_LSB BIT(17) /* 1b */
1750 #define PCIE1_APSRC_REQ_LSB BIT(18) /* 1b */
1751 #define PCIE1_DDREN_REQ_LSB BIT(19) /* 1b */
1752 #define PCIE1_INFRA_REQ_LSB BIT(20) /* 1b */
1753 #define PCIE1_SRCCLKENA_LSB BIT(21) /* 1b */
1754 #define PCIE1_VRF18_REQ_LSB BIT(22) /* 1b */
1755 #define PERISYS_APSRC_REQ_LSB BIT(23) /* 1b */
1756 #define PERISYS_DDREN_REQ_LSB BIT(24) /* 1b */
1757 #define PERISYS_EMI_REQ_LSB BIT(25) /* 1b */
1758 #define PERISYS_INFRA_REQ_LSB BIT(26) /* 1b */
1759 #define PERISYS_PMIC_REQ_LSB BIT(27) /* 1b */
1760 #define PERISYS_SRCCLKENA_LSB BIT(28) /* 1b */
1761 #define PERISYS_VCORE_REQ_LSB BIT(29) /* 1b */
1762 #define PERISYS_VRF18_REQ_LSB BIT(30) /* 1b */
1763 #define SCP_APSRC_REQ_LSB BIT(31) /* 1b */
1765 #define SCP_DDREN_REQ_LSB BIT(0) /* 1b */
1766 #define SCP_EMI_REQ_LSB BIT(1) /* 1b */
1767 #define SCP_INFRA_REQ_LSB BIT(2) /* 1b */
1768 #define SCP_PMIC_REQ_LSB BIT(3) /* 1b */
1769 #define SCP_SRCCLKENA_LSB BIT(4) /* 1b */
1770 #define SCP_VCORE_REQ_LSB BIT(5) /* 1b */
1771 #define SCP_VRF18_REQ_LSB BIT(6) /* 1b */
1772 #define SRCCLKENI_INFRA_REQ_LSB BIT(7) /* 2b */
1773 #define SRCCLKENI_PMIC_REQ_LSB BIT(9) /* 2b */
1774 #define SRCCLKENI_SRCCLKENA_LSB BIT(11) /* 2b */
1775 #define SSPM_APSRC_REQ_LSB BIT(13) /* 1b */
1776 #define SSPM_DDREN_REQ_LSB BIT(14) /* 1b */
1777 #define SSPM_EMI_REQ_LSB BIT(15) /* 1b */
1778 #define SSPM_INFRA_REQ_LSB BIT(16) /* 1b */
1779 #define SSPM_PMIC_REQ_LSB BIT(17) /* 1b */
1780 #define SSPM_SRCCLKENA_LSB BIT(18) /* 1b */
1781 #define SSPM_VRF18_REQ_LSB BIT(19) /* 1b */
1782 #define SSR_APSRC_REQ_LSB BIT(20) /* 1b */
1783 #define SSR_DDREN_REQ_LSB BIT(21) /* 1b */
1784 #define SSR_EMI_REQ_LSB BIT(22) /* 1b */
1785 #define SSR_INFRA_REQ_LSB BIT(23) /* 1b */
1786 #define SSR_PMIC_REQ_LSB BIT(24) /* 1b */
1787 #define SSR_SRCCLKENA_LSB BIT(25) /* 1b */
1788 #define SSR_VRF18_REQ_LSB BIT(26) /* 1b */
1789 #define UFS_APSRC_REQ_LSB BIT(27) /* 1b */
1790 #define UFS_DDREN_REQ_LSB BIT(28) /* 1b */
1791 #define UFS_EMI_REQ_LSB BIT(29) /* 1b */
1792 #define UFS_INFRA_REQ_LSB BIT(30) /* 1b */
1793 #define UFS_PMIC_REQ_LSB BIT(31) /* 1b */
1795 #define UFS_SRCCLKENA_LSB BIT(0) /* 1b */
1796 #define UFS_VRF18_REQ_LSB BIT(1) /* 1b */
1797 #define VDEC_APSRC_REQ_LSB BIT(2) /* 1b */
1798 #define VDEC_DDREN_REQ_LSB BIT(3) /* 1b */
1799 #define VDEC_EMI_REQ_LSB BIT(4) /* 1b */
1800 #define VDEC_INFRA_REQ_LSB BIT(5) /* 1b */
1801 #define VDEC_PMIC_REQ_LSB BIT(6) /* 1b */
1802 #define VDEC_SRCCLKENA_LSB BIT(7) /* 1b */
1803 #define VDEC_VRF18_REQ_LSB BIT(8) /* 1b */
1804 #define VENC_APSRC_REQ_LSB BIT(9) /* 1b */
1805 #define VENC_DDREN_REQ_LSB BIT(10) /* 1b */
1806 #define VENC_EMI_REQ_LSB BIT(11) /* 1b */
1807 #define VENC_INFRA_REQ_LSB BIT(12) /* 1b */
1808 #define VENC_PMIC_REQ_LSB BIT(13) /* 1b */
1809 #define VENC_SRCCLKENA_LSB BIT(14) /* 1b */
1810 #define VENC_VRF18_REQ_LSB BIT(15) /* 1b */
1812 #define SPM2SSPM_WAKEUP_LSB BIT(0) /* 1b */
1813 #define SPM2SCP_WAKEUP_LSB BIT(1) /* 1b */
1814 #define SPM2ADSP_WAKEUP_LSB BIT(2) /* 1b */
1816 #define REG_SW2SPM_WAKEUP_MASK_B_LSB BIT(0) /* 4b */
1817 #define REG_SSPM2SPM_WAKEUP_MASK_B_LSB BIT(4) /* 1b */
1818 #define REG_SCP2SPM_WAKEUP_MASK_B_LSB BIT(5) /* 1b */
1819 #define REG_ADSP2SPM_WAKEUP_MASK_B_LSB BIT(6) /* 1b */
1820 #define SSPM2SPM_WAKEUP_LSB BIT(20) /* 1b */
1821 #define SCP2SPM_WAKEUP_LSB BIT(21) /* 1b */
1822 #define ADSP2SPM_WAKEUP_LSB BIT(22) /* 1b */
1824 #define REG_SRCCLKEN_FAST_RESP_LSB BIT(0) /* 1b */
1825 #define REG_CSYSPWRUP_ACK_MASK_LSB BIT(1) /* 1b */
1827 #define REG_DDREN_DBC_LEN_LSB BIT(0) /* 10b */
1828 #define REG_DDREN_DBC_EN_LSB BIT(16) /* 1b */
1830 #define SPM_VCORE_ACK_WAIT_CYCLE_LSB BIT(0) /* 8b */
1831 #define SPM_PMIC_ACK_WAIT_CYCLE_LSB BIT(8) /* 8b */
1832 #define SPM_SRCCLKENA_ACK_WAIT_CYCLE_LSB BIT(16) /* 8b */
1833 #define SPM_INFRA_ACK_WAIT_CYCLE_LSB BIT(24) /* 8b */
1835 #define SPM_VRF18_ACK_WAIT_CYCLE_LSB BIT(0) /* 8b */
1836 #define SPM_EMI_ACK_WAIT_CYCLE_LSB BIT(8) /* 8b */
1837 #define SPM_APSRC_ACK_WAIT_CYCLE_LSB BIT(16) /* 8b */
1838 #define SPM_DDREN_ACK_WAIT_CYCLE_LSB BIT(24) /* 8b */
1840 #define REG_APU_APSRC_ACK_MASK_LSB BIT(0) /* 1b */
1841 #define REG_APU_DDREN_ACK_MASK_LSB BIT(1) /* 1b */
1842 #define REG_APU_EMI_ACK_MASK_LSB BIT(2) /* 1b */
1843 #define REG_APU_INFRA_ACK_MASK_LSB BIT(3) /* 1b */
1844 #define REG_APU_PMIC_ACK_MASK_LSB BIT(4) /* 1b */
1845 #define REG_APU_SRCCLKENA_ACK_MASK_LSB BIT(5) /* 1b */
1846 #define REG_APU_VRF18_ACK_MASK_LSB BIT(6) /* 1b */
1847 #define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB BIT(7) /* 1b */
1848 #define REG_AUDIO_DSP_DDREN_ACK_MASK_LSB BIT(8) /* 1b */
1849 #define REG_AUDIO_DSP_EMI_ACK_MASK_LSB BIT(9) /* 1b */
1850 #define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB BIT(10) /* 1b */
1851 #define REG_AUDIO_DSP_PMIC_ACK_MASK_LSB BIT(11) /* 1b */
1852 #define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB BIT(12) /* 1b */
1853 #define REG_AUDIO_DSP_VCORE_ACK_MASK_LSB BIT(13) /* 1b */
1854 #define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB BIT(14) /* 1b */
1855 #define REG_CAM_APSRC_ACK_MASK_LSB BIT(15) /* 1b */
1856 #define REG_CAM_DDREN_ACK_MASK_LSB BIT(16) /* 1b */
1857 #define REG_CAM_EMI_ACK_MASK_LSB BIT(17) /* 1b */
1858 #define REG_CAM_INFRA_ACK_MASK_LSB BIT(18) /* 1b */
1859 #define REG_CAM_PMIC_ACK_MASK_LSB BIT(19) /* 1b */
1860 #define REG_CAM_SRCCLKENA_ACK_MASK_LSB BIT(20) /* 1b */
1861 #define REG_CAM_VRF18_ACK_MASK_LSB BIT(21) /* 1b */
1862 #define REG_CCU_APSRC_ACK_MASK_LSB BIT(22) /* 1b */
1863 #define REG_CCU_DDREN_ACK_MASK_LSB BIT(23) /* 1b */
1864 #define REG_CCU_EMI_ACK_MASK_LSB BIT(24) /* 1b */
1865 #define REG_CCU_INFRA_ACK_MASK_LSB BIT(25) /* 1b */
1866 #define REG_CCU_PMIC_ACK_MASK_LSB BIT(26) /* 1b */
1867 #define REG_CCU_SRCCLKENA_ACK_MASK_LSB BIT(27) /* 1b */
1868 #define REG_CCU_VRF18_ACK_MASK_LSB BIT(28) /* 1b */
1869 #define REG_CONN_APSRC_ACK_MASK_LSB BIT(29) /* 1b */
1870 #define REG_CONN_DDREN_ACK_MASK_LSB BIT(30) /* 1b */
1871 #define REG_CONN_EMI_ACK_MASK_LSB BIT(31) /* 1b */
1873 #define REG_CONN_INFRA_ACK_MASK_LSB BIT(0) /* 1b */
1874 #define REG_CONN_PMIC_ACK_MASK_LSB BIT(1) /* 1b */
1875 #define REG_CONN_SRCCLKENA_ACK_MASK_LSB BIT(2) /* 1b */
1876 #define REG_CONN_VCORE_ACK_MASK_LSB BIT(3) /* 1b */
1877 #define REG_CONN_VRF18_ACK_MASK_LSB BIT(4) /* 1b */
1878 #define REG_CPUEB_APSRC_ACK_MASK_LSB BIT(5) /* 1b */
1879 #define REG_CPUEB_DDREN_ACK_MASK_LSB BIT(6) /* 1b */
1880 #define REG_CPUEB_EMI_ACK_MASK_LSB BIT(7) /* 1b */
1881 #define REG_CPUEB_INFRA_ACK_MASK_LSB BIT(8) /* 1b */
1882 #define REG_CPUEB_PMIC_ACK_MASK_LSB BIT(9) /* 1b */
1883 #define REG_CPUEB_SRCCLKENA_ACK_MASK_LSB BIT(10) /* 1b */
1884 #define REG_CPUEB_VRF18_ACK_MASK_LSB BIT(11) /* 1b */
1885 #define REG_DISP0_APSRC_ACK_MASK_LSB BIT(12) /* 1b */
1886 #define REG_DISP0_DDREN_ACK_MASK_LSB BIT(13) /* 1b */
1887 #define REG_DISP0_EMI_ACK_MASK_LSB BIT(14) /* 1b */
1888 #define REG_DISP0_INFRA_ACK_MASK_LSB BIT(15) /* 1b */
1889 #define REG_DISP0_PMIC_ACK_MASK_LSB BIT(16) /* 1b */
1890 #define REG_DISP0_SRCCLKENA_ACK_MASK_LSB BIT(17) /* 1b */
1891 #define REG_DISP0_VRF18_ACK_MASK_LSB BIT(18) /* 1b */
1892 #define REG_DISP1_APSRC_ACK_MASK_LSB BIT(19) /* 1b */
1893 #define REG_DISP1_DDREN_ACK_MASK_LSB BIT(20) /* 1b */
1894 #define REG_DISP1_EMI_ACK_MASK_LSB BIT(21) /* 1b */
1895 #define REG_DISP1_INFRA_ACK_MASK_LSB BIT(22) /* 1b */
1896 #define REG_DISP1_PMIC_ACK_MASK_LSB BIT(23) /* 1b */
1897 #define REG_DISP1_SRCCLKENA_ACK_MASK_LSB BIT(24) /* 1b */
1898 #define REG_DISP1_VRF18_ACK_MASK_LSB BIT(25) /* 1b */
1899 #define REG_DPM_APSRC_ACK_MASK_LSB BIT(26) /* 4b */
1901 #define REG_DPM_DDREN_ACK_MASK_LSB BIT(0) /* 4b */
1902 #define REG_DPM_EMI_ACK_MASK_LSB BIT(4) /* 4b */
1903 #define REG_DPM_INFRA_ACK_MASK_LSB BIT(8) /* 4b */
1904 #define REG_DPM_PMIC_ACK_MASK_LSB BIT(12) /* 4b */
1905 #define REG_DPM_SRCCLKENA_ACK_MASK_LSB BIT(16) /* 4b */
1906 #define REG_DPM_VCORE_ACK_MASK_LSB BIT(20) /* 4b */
1907 #define REG_DPM_VRF18_ACK_MASK_LSB BIT(24) /* 4b */
1908 #define REG_EMISYS_APSRC_ACK_MASK_LSB BIT(28) /* 1b */
1909 #define REG_EMISYS_DDREN_ACK_MASK_LSB BIT(29) /* 1b */
1910 #define REG_EMISYS_EMI_ACK_MASK_LSB BIT(30) /* 1b */
1911 #define REG_GCE_D_APSRC_ACK_MASK_LSB BIT(31) /* 1b */
1913 #define REG_GCE_D_DDREN_ACK_MASK_LSB BIT(0) /* 1b */
1914 #define REG_GCE_D_EMI_ACK_MASK_LSB BIT(1) /* 1b */
1915 #define REG_GCE_D_INFRA_ACK_MASK_LSB BIT(2) /* 1b */
1916 #define REG_GCE_D_PMIC_ACK_MASK_LSB BIT(3) /* 1b */
1917 #define REG_GCE_D_SRCCLKENA_ACK_MASK_LSB BIT(4) /* 1b */
1918 #define REG_GCE_D_VRF18_ACK_MASK_LSB BIT(5) /* 1b */
1919 #define REG_GCE_M_APSRC_ACK_MASK_LSB BIT(6) /* 1b */
1920 #define REG_GCE_M_DDREN_ACK_MASK_LSB BIT(7) /* 1b */
1921 #define REG_GCE_M_EMI_ACK_MASK_LSB BIT(8) /* 1b */
1922 #define REG_GCE_M_INFRA_ACK_MASK_LSB BIT(9) /* 1b */
1923 #define REG_GCE_M_PMIC_ACK_MASK_LSB BIT(10) /* 1b */
1924 #define REG_GCE_M_SRCCLKENA_ACK_MASK_LSB BIT(11) /* 1b */
1925 #define REG_GCE_M_VRF18_ACK_MASK_LSB BIT(12) /* 1b */
1926 #define REG_GPUEB_APSRC_ACK_MASK_LSB BIT(13) /* 1b */
1927 #define REG_GPUEB_DDREN_ACK_MASK_LSB BIT(14) /* 1b */
1928 #define REG_GPUEB_EMI_ACK_MASK_LSB BIT(15) /* 1b */
1929 #define REG_GPUEB_INFRA_ACK_MASK_LSB BIT(16) /* 1b */
1930 #define REG_GPUEB_PMIC_ACK_MASK_LSB BIT(17) /* 1b */
1931 #define REG_GPUEB_SRCCLKENA_ACK_MASK_LSB BIT(18) /* 1b */
1932 #define REG_GPUEB_VRF18_ACK_MASK_LSB BIT(19) /* 1b */
1933 #define REG_HWCCF_APSRC_ACK_MASK_LSB BIT(20) /* 1b */
1934 #define REG_HWCCF_DDREN_ACK_MASK_LSB BIT(21) /* 1b */
1935 #define REG_HWCCF_EMI_ACK_MASK_LSB BIT(22) /* 1b */
1936 #define REG_HWCCF_INFRA_ACK_MASK_LSB BIT(23) /* 1b */
1937 #define REG_HWCCF_PMIC_ACK_MASK_LSB BIT(24) /* 1b */
1938 #define REG_HWCCF_SRCCLKENA_ACK_MASK_LSB BIT(25) /* 1b */
1939 #define REG_HWCCF_VCORE_ACK_MASK_LSB BIT(26) /* 1b */
1940 #define REG_HWCCF_VRF18_ACK_MASK_LSB BIT(27) /* 1b */
1941 #define REG_IMG_APSRC_ACK_MASK_LSB BIT(28) /* 1b */
1942 #define REG_IMG_DDREN_ACK_MASK_LSB BIT(29) /* 1b */
1943 #define REG_IMG_EMI_ACK_MASK_LSB BIT(30) /* 1b */
1944 #define REG_IMG_INFRA_ACK_MASK_LSB BIT(31) /* 1b */
1946 #define REG_IMG_PMIC_ACK_MASK_LSB BIT(0) /* 1b */
1947 #define REG_IMG_SRCCLKENA_ACK_MASK_LSB BIT(1) /* 1b */
1948 #define REG_IMG_VRF18_ACK_MASK_LSB BIT(2) /* 1b */
1949 #define REG_MCU_APSRC_ACK_MASK_LSB BIT(3) /* 1b */
1950 #define REG_MCU_DDREN_ACK_MASK_LSB BIT(4) /* 1b */
1951 #define REG_MCU_EMI_ACK_MASK_LSB BIT(5) /* 1b */
1952 #define REG_MD_APSRC_ACK_MASK_LSB BIT(6) /* 1b */
1953 #define REG_MD_DDREN_ACK_MASK_LSB BIT(7) /* 1b */
1954 #define REG_MD_EMI_ACK_MASK_LSB BIT(8) /* 1b */
1955 #define REG_MD_INFRA_ACK_MASK_LSB BIT(9) /* 1b */
1956 #define REG_MD_PMIC_ACK_MASK_LSB BIT(10) /* 1b */
1957 #define REG_MD_SRCCLKENA_ACK_MASK_LSB BIT(11) /* 1b */
1958 #define REG_MD_VCORE_ACK_MASK_LSB BIT(12) /* 1b */
1959 #define REG_MD_VRF18_ACK_MASK_LSB BIT(13) /* 1b */
1960 #define REG_MM_PROC_APSRC_ACK_MASK_LSB BIT(14) /* 1b */
1961 #define REG_MM_PROC_DDREN_ACK_MASK_LSB BIT(15) /* 1b */
1962 #define REG_MM_PROC_EMI_ACK_MASK_LSB BIT(16) /* 1b */
1963 #define REG_MM_PROC_INFRA_ACK_MASK_LSB BIT(17) /* 1b */
1964 #define REG_MM_PROC_PMIC_ACK_MASK_LSB BIT(18) /* 1b */
1965 #define REG_MM_PROC_SRCCLKENA_ACK_MASK_LSB BIT(19) /* 1b */
1966 #define REG_MM_PROC_VRF18_ACK_MASK_LSB BIT(20) /* 1b */
1967 #define REG_PCIE0_APSRC_ACK_MASK_LSB BIT(21) /* 1b */
1968 #define REG_PCIE0_DDREN_ACK_MASK_LSB BIT(22) /* 1b */
1969 #define REG_PCIE0_INFRA_ACK_MASK_LSB BIT(23) /* 1b */
1970 #define REG_PCIE0_SRCCLKENA_ACK_MASK_LSB BIT(24) /* 1b */
1971 #define REG_PCIE0_VRF18_ACK_MASK_LSB BIT(25) /* 1b */
1972 #define REG_PCIE1_APSRC_ACK_MASK_LSB BIT(26) /* 1b */
1973 #define REG_PCIE1_DDREN_ACK_MASK_LSB BIT(27) /* 1b */
1974 #define REG_PCIE1_INFRA_ACK_MASK_LSB BIT(28) /* 1b */
1975 #define REG_PCIE1_SRCCLKENA_ACK_MASK_LSB BIT(29) /* 1b */
1976 #define REG_PCIE1_VRF18_ACK_MASK_LSB BIT(30) /* 1b */
1977 #define REG_PERISYS_APSRC_ACK_MASK_LSB BIT(31) /* 1b */
1979 #define REG_PERISYS_DDREN_ACK_MASK_LSB BIT(0) /* 1b */
1980 #define REG_PERISYS_EMI_ACK_MASK_LSB BIT(1) /* 1b */
1981 #define REG_PERISYS_INFRA_ACK_MASK_LSB BIT(2) /* 1b */
1982 #define REG_PERISYS_PMIC_ACK_MASK_LSB BIT(3) /* 1b */
1983 #define REG_PERISYS_SRCCLKENA_ACK_MASK_LSB BIT(4) /* 1b */
1984 #define REG_PERISYS_VCORE_ACK_MASK_LSB BIT(5) /* 1b */
1985 #define REG_PERISYS_VRF18_ACK_MASK_LSB BIT(6) /* 1b */
1986 #define REG_SCP_APSRC_ACK_MASK_LSB BIT(7) /* 1b */
1987 #define REG_SCP_DDREN_ACK_MASK_LSB BIT(8) /* 1b */
1988 #define REG_SCP_EMI_ACK_MASK_LSB BIT(9) /* 1b */
1989 #define REG_SCP_INFRA_ACK_MASK_LSB BIT(10) /* 1b */
1990 #define REG_SCP_PMIC_ACK_MASK_LSB BIT(11) /* 1b */
1991 #define REG_SCP_SRCCLKENA_ACK_MASK_LSB BIT(12) /* 1b */
1992 #define REG_SCP_VCORE_ACK_MASK_LSB BIT(13) /* 1b */
1993 #define REG_SCP_VRF18_ACK_MASK_LSB BIT(14) /* 1b */
1994 #define REG_SSPM_APSRC_ACK_MASK_LSB BIT(15) /* 1b */
1995 #define REG_SSPM_DDREN_ACK_MASK_LSB BIT(16) /* 1b */
1996 #define REG_SSPM_EMI_ACK_MASK_LSB BIT(17) /* 1b */
1997 #define REG_SSPM_INFRA_ACK_MASK_LSB BIT(18) /* 1b */
1998 #define REG_SSPM_PMIC_ACK_MASK_LSB BIT(19) /* 1b */
1999 #define REG_SSPM_SRCCLKENA_ACK_MASK_LSB BIT(20) /* 1b */
2000 #define REG_SSPM_VRF18_ACK_MASK_LSB BIT(21) /* 1b */
2001 #define REG_SSR_APSRC_ACK_MASK_LSB BIT(22) /* 1b */
2002 #define REG_SSR_DDREN_ACK_MASK_LSB BIT(23) /* 1b */
2003 #define REG_SSR_EMI_ACK_MASK_LSB BIT(24) /* 1b */
2004 #define REG_SSR_INFRA_ACK_MASK_LSB BIT(25) /* 1b */
2005 #define REG_SSR_PMIC_ACK_MASK_LSB BIT(26) /* 1b */
2006 #define REG_SSR_SRCCLKENA_ACK_MASK_LSB BIT(27) /* 1b */
2007 #define REG_SSR_VRF18_ACK_MASK_LSB BIT(28) /* 1b */
2008 #define REG_UFS_APSRC_ACK_MASK_LSB BIT(29) /* 1b */
2009 #define REG_UFS_DDREN_ACK_MASK_LSB BIT(30) /* 1b */
2010 #define REG_UFS_EMI_ACK_MASK_LSB BIT(31) /* 1b */
2012 #define REG_UFS_INFRA_ACK_MASK_LSB BIT(0) /* 1b */
2013 #define REG_UFS_PMIC_ACK_MASK_LSB BIT(1) /* 1b */
2014 #define REG_UFS_SRCCLKENA_ACK_MASK_LSB BIT(2) /* 1b */
2015 #define REG_UFS_VRF18_ACK_MASK_LSB BIT(3) /* 1b */
2016 #define REG_VDEC_APSRC_ACK_MASK_LSB BIT(4) /* 1b */
2017 #define REG_VDEC_DDREN_ACK_MASK_LSB BIT(5) /* 1b */
2018 #define REG_VDEC_EMI_ACK_MASK_LSB BIT(6) /* 1b */
2019 #define REG_VDEC_INFRA_ACK_MASK_LSB BIT(7) /* 1b */
2020 #define REG_VDEC_PMIC_ACK_MASK_LSB BIT(8) /* 1b */
2021 #define REG_VDEC_SRCCLKENA_ACK_MASK_LSB BIT(9) /* 1b */
2022 #define REG_VDEC_VRF18_ACK_MASK_LSB BIT(10) /* 1b */
2023 #define REG_VENC_APSRC_ACK_MASK_LSB BIT(11) /* 1b */
2024 #define REG_VENC_DDREN_ACK_MASK_LSB BIT(12) /* 1b */
2025 #define REG_VENC_EMI_ACK_MASK_LSB BIT(13) /* 1b */
2026 #define REG_VENC_INFRA_ACK_MASK_LSB BIT(14) /* 1b */
2027 #define REG_VENC_PMIC_ACK_MASK_LSB BIT(15) /* 1b */
2028 #define REG_VENC_SRCCLKENA_ACK_MASK_LSB BIT(16) /* 1b */
2029 #define REG_VENC_VRF18_ACK_MASK_LSB BIT(17) /* 1b */
2031 #define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(0) /* 1b */
2033 #define SPM_VCORE_SLEEP_COUNT_LSB BIT(0) /* 16b */
2034 #define SPM_VCORE_WAKE_COUNT_LSB BIT(16) /* 16b */
2036 #define SPM_PMIC_SLEEP_COUNT_LSB BIT(0) /* 16b */
2037 #define SPM_PMIC_WAKE_COUNT_LSB BIT(16) /* 16b */
2039 #define SPM_SRCCLKENA_SLEEP_COUNT_LSB BIT(0) /* 16b */
2040 #define SPM_SRCCLKENA_WAKE_COUNT_LSB BIT(16) /* 16b */
2042 #define SPM_INFRA_SLEEP_COUNT_LSB BIT(0) /* 16b */
2043 #define SPM_INFRA_WAKE_COUNT_LSB BIT(16) /* 16b */
2045 #define SPM_VRF18_SLEEP_COUNT_LSB BIT(0) /* 16b */
2046 #define SPM_VRF18_WAKE_COUNT_LSB BIT(16) /* 16b */
2048 #define SPM_EMI_SLEEP_COUNT_LSB BIT(0) /* 16b */
2049 #define SPM_EMI_WAKE_COUNT_LSB BIT(16) /* 16b */
2051 #define SPM_APSRC_SLEEP_COUNT_LSB BIT(0) /* 16b */
2052 #define SPM_APSRC_WAKE_COUNT_LSB BIT(16) /* 16b */
2054 #define SPM_DDREN_SLEEP_COUNT_LSB BIT(0) /* 16b */
2055 #define SPM_DDREN_WAKE_COUNT_LSB BIT(16) /* 16b */
2057 #define PCM_WDT_LATCH_0_LSB BIT(0) /* 32b */
2059 #define PCM_WDT_LATCH_1_LSB BIT(0) /* 32b */
2061 #define PCM_WDT_LATCH_2_LSB BIT(0) /* 32b */
2063 #define PCM_WDT_LATCH_3_LSB BIT(0) /* 32b */
2065 #define PCM_WDT_LATCH_4_LSB BIT(0) /* 32b */
2067 #define PCM_WDT_LATCH_5_LSB BIT(0) /* 32b */
2069 #define PCM_WDT_LATCH_6_LSB BIT(0) /* 32b */
2071 #define PCM_WDT_LATCH_7_LSB BIT(0) /* 32b */
2073 #define PCM_WDT_LATCH_8_LSB BIT(0) /* 32b */
2075 #define PCM_WDT_LATCH_9_LSB BIT(0) /* 32b */
2077 #define PCM_WDT_LATCH_10_LSB BIT(0) /* 32b */
2079 #define PCM_WDT_LATCH_11_LSB BIT(0) /* 32b */
2081 #define PCM_WDT_LATCH_12_LSB BIT(0) /* 32b */
2083 #define PCM_WDT_LATCH_13_LSB BIT(0) /* 32b */
2085 #define PCM_WDT_LATCH_14_LSB BIT(0) /* 32b */
2087 #define PCM_WDT_LATCH_15_LSB BIT(0) /* 32b */
2089 #define PCM_WDT_LATCH_16_LSB BIT(0) /* 32b */
2091 #define PCM_WDT_LATCH_17_LSB BIT(0) /* 32b */
2093 #define PCM_WDT_LATCH_18_LSB BIT(0) /* 32b */
2095 #define PCM_WDT_LATCH_19_LSB BIT(0) /* 32b */
2097 #define PCM_WDT_LATCH_20_LSB BIT(0) /* 32b */
2099 #define PCM_WDT_LATCH_21_LSB BIT(0) /* 32b */
2101 #define PCM_WDT_LATCH_22_LSB BIT(0) /* 32b */
2103 #define PCM_WDT_LATCH_23_LSB BIT(0) /* 32b */
2105 #define PCM_WDT_LATCH_24_LSB BIT(0) /* 32b */
2107 #define PCM_WDT_LATCH_25_LSB BIT(0) /* 32b */
2109 #define PCM_WDT_LATCH_26_LSB BIT(0) /* 32b */
2111 #define PCM_WDT_LATCH_27_LSB BIT(0) /* 32b */
2113 #define PCM_WDT_LATCH_28_LSB BIT(0) /* 32b */
2115 #define PCM_WDT_LATCH_29_LSB BIT(0) /* 32b */
2117 #define PCM_WDT_LATCH_30_LSB BIT(0) /* 32b */
2119 #define PCM_WDT_LATCH_31_LSB BIT(0) /* 32b */
2121 #define PCM_WDT_LATCH_32_LSB BIT(0) /* 32b */
2123 #define PCM_WDT_LATCH_33_LSB BIT(0) /* 32b */
2125 #define PCM_WDT_LATCH_34_LSB BIT(0) /* 32b */
2127 #define PCM_WDT_LATCH_35_LSB BIT(0) /* 32b */
2129 #define PCM_WDT_LATCH_36_LSB BIT(0) /* 32b */
2131 #define PCM_WDT_LATCH_37_LSB BIT(0) /* 32b */
2133 #define PCM_WDT_LATCH_38_LSB BIT(0) /* 32b */
2135 #define PCM_WDT_LATCH_39_LSB BIT(0) /* 32b */
2137 #define PCM_WDT_LATCH_40_LSB BIT(0) /* 32b */
2139 #define PCM_WDT_LATCH_SPARE_0_LSB BIT(0) /* 32b */
2141 #define PCM_WDT_LATCH_SPARE_1_LSB BIT(0) /* 32b */
2143 #define PCM_WDT_LATCH_SPARE_2_LSB BIT(0) /* 32b */
2145 #define PCM_WDT_LATCH_SPARE_3_LSB BIT(0) /* 32b */
2147 #define PCM_WDT_LATCH_SPARE_4_LSB BIT(0) /* 32b */
2149 #define PCM_WDT_LATCH_SPARE_5_LSB BIT(0) /* 32b */
2151 #define PCM_WDT_LATCH_SPARE_6_LSB BIT(0) /* 32b */
2153 #define PCM_WDT_LATCH_SPARE_7_LSB BIT(0) /* 32b */
2155 #define PCM_WDT_LATCH_SPARE_8_LSB BIT(0) /* 32b */
2157 #define PCM_WDT_LATCH_SPARE_9_LSB BIT(0) /* 32b */
2159 #define DRAMC_GATING_ERR_LATCH_0_LSB BIT(0) /* 32b */
2161 #define DRAMC_GATING_ERR_LATCH_1_LSB BIT(0) /* 32b */
2163 #define DRAMC_GATING_ERR_LATCH_2_LSB BIT(0) /* 32b */
2165 #define DRAMC_GATING_ERR_LATCH_3_LSB BIT(0) /* 32b */
2167 #define DRAMC_GATING_ERR_LATCH_4_LSB BIT(0) /* 32b */
2169 #define DRAMC_GATING_ERR_LATCH_5_LSB BIT(0) /* 32b */
2171 #define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB BIT(0) /* 32b */
2173 #define SPM_DEBUG_OUT_ENABLE_LSB BIT(0) /* 1b */
2175 #define SPM_ACK_CHK_SW_EN_0_LSB BIT(0) /* 1b */
2176 #define SPM_ACK_CHK_CLR_ALL_0_LSB BIT(1) /* 1b */
2177 #define SPM_ACK_CHK_CLR_TIMER_0_LSB BIT(2) /* 1b */
2178 #define SPM_ACK_CHK_CLR_IRQ_0_LSB BIT(3) /* 1b */
2179 #define SPM_ACK_CHK_STA_EN_0_LSB BIT(4) /* 1b */
2180 #define SPM_ACK_CHK_WAKEUP_EN_0_LSB BIT(5) /* 1b */
2181 #define SPM_ACK_CHK_WDT_EN_0_LSB BIT(6) /* 1b */
2182 #define SPM_ACK_CHK_SWINT_EN_0_LSB BIT(7) /* 1b */
2183 #define SPM_ACK_CHK_HW_EN_0_LSB BIT(8) /* 1b */
2184 #define SPM_ACK_CHK_HW_MODE_0_LSB BIT(9) /* 3b */
2185 #define SPM_ACK_CHK_FAIL_0_LSB BIT(15) /* 1b */
2187 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB BIT(0) /* 5b */
2188 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB BIT(5) /* 3b */
2189 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB BIT(16) /* 5b */
2190 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB BIT(21) /* 3b */
2192 #define SPM_ACK_CHK_TIMER_VAL_0_LSB BIT(0) /* 16b */
2193 #define SPM_ACK_CHK_TIMER_0_LSB BIT(16) /* 16b */
2195 #define SPM_ACK_CHK_STA_0_LSB BIT(0) /* 32b */
2197 #define SPM_ACK_CHK_SW_EN_1_LSB BIT(0) /* 1b */
2198 #define SPM_ACK_CHK_CLR_ALL_1_LSB BIT(1) /* 1b */
2199 #define SPM_ACK_CHK_CLR_TIMER_1_LSB BIT(2) /* 1b */
2200 #define SPM_ACK_CHK_CLR_IRQ_1_LSB BIT(3) /* 1b */
2201 #define SPM_ACK_CHK_STA_EN_1_LSB BIT(4) /* 1b */
2202 #define SPM_ACK_CHK_WAKEUP_EN_1_LSB BIT(5) /* 1b */
2203 #define SPM_ACK_CHK_WDT_EN_1_LSB BIT(6) /* 1b */
2204 #define SPM_ACK_CHK_SWINT_EN_1_LSB BIT(7) /* 1b */
2205 #define SPM_ACK_CHK_HW_EN_1_LSB BIT(8) /* 1b */
2206 #define SPM_ACK_CHK_HW_MODE_1_LSB BIT(9) /* 3b */
2207 #define SPM_ACK_CHK_FAIL_1_LSB BIT(15) /* 1b */
2209 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB BIT(0) /* 5b */
2210 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB BIT(5) /* 3b */
2211 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB BIT(16) /* 5b */
2212 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB BIT(21) /* 3b */
2214 #define SPM_ACK_CHK_TIMER_VAL_1_LSB BIT(0) /* 16b */
2215 #define SPM_ACK_CHK_TIMER_1_LSB BIT(16) /* 16b */
2217 #define SPM_ACK_CHK_STA_1_LSB BIT(0) /* 32b */
2219 #define SPM_ACK_CHK_SW_EN_2_LSB BIT(0) /* 1b */
2220 #define SPM_ACK_CHK_CLR_ALL_2_LSB BIT(1) /* 1b */
2221 #define SPM_ACK_CHK_CLR_TIMER_2_LSB BIT(2) /* 1b */
2222 #define SPM_ACK_CHK_CLR_IRQ_2_LSB BIT(3) /* 1b */
2223 #define SPM_ACK_CHK_STA_EN_2_LSB BIT(4) /* 1b */
2224 #define SPM_ACK_CHK_WAKEUP_EN_2_LSB BIT(5) /* 1b */
2225 #define SPM_ACK_CHK_WDT_EN_2_LSB BIT(6) /* 1b */
2226 #define SPM_ACK_CHK_SWINT_EN_2_LSB BIT(7) /* 1b */
2227 #define SPM_ACK_CHK_HW_EN_2_LSB BIT(8) /* 1b */
2228 #define SPM_ACK_CHK_HW_MODE_2_LSB BIT(9) /* 3b */
2229 #define SPM_ACK_CHK_FAIL_2_LSB BIT(15) /* 1b */
2231 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB BIT(0) /* 5b */
2232 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB BIT(5) /* 3b */
2233 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB BIT(16) /* 5b */
2234 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB BIT(21) /* 3b */
2236 #define SPM_ACK_CHK_TIMER_VAL_2_LSB BIT(0) /* 16b */
2237 #define SPM_ACK_CHK_TIMER_2_LSB BIT(16) /* 16b */
2239 #define SPM_ACK_CHK_STA_2_LSB BIT(0) /* 32b */
2241 #define SPM_ACK_CHK_SW_EN_3_LSB BIT(0) /* 1b */
2242 #define SPM_ACK_CHK_CLR_ALL_3_LSB BIT(1) /* 1b */
2243 #define SPM_ACK_CHK_CLR_TIMER_3_LSB BIT(2) /* 1b */
2244 #define SPM_ACK_CHK_CLR_IRQ_3_LSB BIT(3) /* 1b */
2245 #define SPM_ACK_CHK_STA_EN_3_LSB BIT(4) /* 1b */
2246 #define SPM_ACK_CHK_WAKEUP_EN_3_LSB BIT(5) /* 1b */
2247 #define SPM_ACK_CHK_WDT_EN_3_LSB BIT(6) /* 1b */
2248 #define SPM_ACK_CHK_SWINT_EN_3_LSB BIT(7) /* 1b */
2249 #define SPM_ACK_CHK_HW_EN_3_LSB BIT(8) /* 1b */
2250 #define SPM_ACK_CHK_HW_MODE_3_LSB BIT(9) /* 3b */
2251 #define SPM_ACK_CHK_FAIL_3_LSB BIT(15) /* 1b */
2253 #define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB BIT(0) /* 5b */
2254 #define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB BIT(5) /* 3b */
2255 #define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB BIT(16) /* 5b */
2256 #define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB BIT(21) /* 3b */
2258 #define MD1_PWR_RST_B_LSB BIT(0) /* 1b */
2259 #define MD1_PWR_ISO_LSB BIT(1) /* 1b */
2260 #define MD1_PWR_ON_LSB BIT(2) /* 1b */
2261 #define MD1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2262 #define MD1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2263 #define MD1_RTFF_SAVE_LSB BIT(24) /* 1b */
2264 #define MD1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2265 #define MD1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2266 #define SC_MD1_PWR_ACK_LSB BIT(30) /* 1b */
2267 #define SC_MD1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2269 #define CONN_PWR_RST_B_LSB BIT(0) /* 1b */
2270 #define CONN_PWR_ISO_LSB BIT(1) /* 1b */
2271 #define CONN_PWR_ON_LSB BIT(2) /* 1b */
2272 #define CONN_PWR_ON_2ND_LSB BIT(3) /* 1b */
2273 #define CONN_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2274 #define CONN_RTFF_SAVE_LSB BIT(24) /* 1b */
2275 #define CONN_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2276 #define CONN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2277 #define SC_CONN_PWR_ACK_LSB BIT(30) /* 1b */
2278 #define SC_CONN_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2280 #define IFR_PWR_RST_B_LSB BIT(0) /* 1b */
2281 #define IFR_PWR_ISO_LSB BIT(1) /* 1b */
2282 #define IFR_PWR_ON_LSB BIT(2) /* 1b */
2283 #define IFR_PWR_ON_2ND_LSB BIT(3) /* 1b */
2284 #define IFR_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2285 #define IFR_SRAM_CKISO_LSB BIT(5) /* 1b */
2286 #define IFR_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2287 #define IFR_SRAM_PDN_LSB BIT(8) /* 1b */
2288 #define IFR_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2289 #define SC_IFR_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2290 #define SC_IFR_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2291 #define IFR_RTFF_SAVE_LSB BIT(24) /* 1b */
2292 #define IFR_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2293 #define IFR_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2294 #define SC_IFR_PWR_ACK_LSB BIT(30) /* 1b */
2295 #define SC_IFR_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2297 #define PERI_PWR_RST_B_LSB BIT(0) /* 1b */
2298 #define PERI_PWR_ISO_LSB BIT(1) /* 1b */
2299 #define PERI_PWR_ON_LSB BIT(2) /* 1b */
2300 #define PERI_PWR_ON_2ND_LSB BIT(3) /* 1b */
2301 #define PERI_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2302 #define PERI_SRAM_CKISO_LSB BIT(5) /* 1b */
2303 #define PERI_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2304 #define PERI_SRAM_PDN_LSB BIT(8) /* 1b */
2305 #define PERI_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2306 #define SC_PERI_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2307 #define SC_PERI_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2308 #define PERI_RTFF_SAVE_LSB BIT(24) /* 1b */
2309 #define PERI_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2310 #define PERI_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2311 #define SC_PERI_PWR_ACK_LSB BIT(30) /* 1b */
2312 #define SC_PERI_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2314 #define UFS0_PWR_RST_B_LSB BIT(0) /* 1b */
2315 #define UFS0_PWR_ISO_LSB BIT(1) /* 1b */
2316 #define UFS0_PWR_ON_LSB BIT(2) /* 1b */
2317 #define UFS0_PWR_ON_2ND_LSB BIT(3) /* 1b */
2318 #define UFS0_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2319 #define UFS0_SRAM_CKISO_LSB BIT(5) /* 1b */
2320 #define UFS0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2321 #define UFS0_SRAM_PDN_LSB BIT(8) /* 1b */
2322 #define UFS0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2323 #define SC_UFS0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2324 #define SC_UFS0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2325 #define UFS0_RTFF_SAVE_LSB BIT(24) /* 1b */
2326 #define UFS0_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2327 #define UFS0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2328 #define SC_UFS0_PWR_ACK_LSB BIT(30) /* 1b */
2329 #define SC_UFS0_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2331 #define UFS0_PHY_PWR_RST_B_LSB BIT(0) /* 1b */
2332 #define UFS0_PHY_PWR_ISO_LSB BIT(1) /* 1b */
2333 #define UFS0_PHY_PWR_ON_LSB BIT(2) /* 1b */
2334 #define UFS0_PHY_PWR_ON_2ND_LSB BIT(3) /* 1b */
2335 #define UFS0_PHY_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2336 #define UFS0_PHY_RTFF_SAVE_LSB BIT(24) /* 1b */
2337 #define UFS0_PHY_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2338 #define UFS0_PHY_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2339 #define SC_UFS0_PHY_PWR_ACK_LSB BIT(30) /* 1b */
2340 #define SC_UFS0_PHY_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2342 #define AUDIO_PWR_RST_B_LSB BIT(0) /* 1b */
2343 #define AUDIO_PWR_ISO_LSB BIT(1) /* 1b */
2344 #define AUDIO_PWR_ON_LSB BIT(2) /* 1b */
2345 #define AUDIO_PWR_ON_2ND_LSB BIT(3) /* 1b */
2346 #define AUDIO_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2347 #define AUDIO_SRAM_PDN_LSB BIT(8) /* 1b */
2348 #define SC_AUDIO_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2349 #define AUDIO_RTFF_SAVE_LSB BIT(24) /* 1b */
2350 #define AUDIO_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2351 #define AUDIO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2352 #define SC_AUDIO_PWR_ACK_LSB BIT(30) /* 1b */
2353 #define SC_AUDIO_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2355 #define ADSP_TOP_PWR_RST_B_LSB BIT(0) /* 1b */
2356 #define ADSP_TOP_PWR_ISO_LSB BIT(1) /* 1b */
2357 #define ADSP_TOP_PWR_ON_LSB BIT(2) /* 1b */
2358 #define ADSP_TOP_PWR_ON_2ND_LSB BIT(3) /* 1b */
2359 #define ADSP_TOP_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2360 #define ADSP_TOP_SRAM_CKISO_LSB BIT(5) /* 1b */
2361 #define ADSP_TOP_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2362 #define ADSP_TOP_SRAM_PDN_LSB BIT(8) /* 1b */
2363 #define ADSP_TOP_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2364 #define SC_ADSP_TOP_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2365 #define SC_ADSP_TOP_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2366 #define ADSP_TOP_RTFF_SAVE_LSB BIT(24) /* 1b */
2367 #define ADSP_TOP_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2368 #define ADSP_TOP_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2369 #define SC_ADSP_TOP_PWR_ACK_LSB BIT(30) /* 1b */
2370 #define SC_ADSP_TOP_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2372 #define ADSP_INFRA_PWR_RST_B_LSB BIT(0) /* 1b */
2373 #define ADSP_INFRA_PWR_ISO_LSB BIT(1) /* 1b */
2374 #define ADSP_INFRA_PWR_ON_LSB BIT(2) /* 1b */
2375 #define ADSP_INFRA_PWR_ON_2ND_LSB BIT(3) /* 1b */
2376 #define ADSP_INFRA_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2377 #define ADSP_INFRA_RTFF_SAVE_LSB BIT(24) /* 1b */
2378 #define ADSP_INFRA_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2379 #define ADSP_INFRA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2380 #define SC_ADSP_INFRA_PWR_ACK_LSB BIT(30) /* 1b */
2381 #define SC_ADSP_INFRA_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2383 #define ADSP_AO_PWR_RST_B_LSB BIT(0) /* 1b */
2384 #define ADSP_AO_PWR_ISO_LSB BIT(1) /* 1b */
2385 #define ADSP_AO_PWR_ON_LSB BIT(2) /* 1b */
2386 #define ADSP_AO_PWR_ON_2ND_LSB BIT(3) /* 1b */
2387 #define ADSP_AO_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2388 #define ADSP_AO_RTFF_SAVE_LSB BIT(24) /* 1b */
2389 #define ADSP_AO_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2390 #define ADSP_AO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2391 #define SC_ADSP_AO_PWR_ACK_LSB BIT(30) /* 1b */
2392 #define SC_ADSP_AO_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2394 #define ISP_MAIN_PWR_RST_B_LSB BIT(0) /* 1b */
2395 #define ISP_MAIN_PWR_ISO_LSB BIT(1) /* 1b */
2396 #define ISP_MAIN_PWR_ON_LSB BIT(2) /* 1b */
2397 #define ISP_MAIN_PWR_ON_2ND_LSB BIT(3) /* 1b */
2398 #define ISP_MAIN_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2399 #define ISP_MAIN_SRAM_PDN_LSB BIT(8) /* 1b */
2400 #define SC_ISP_MAIN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2401 #define ISP_MAIN_RTFF_SAVE_LSB BIT(24) /* 1b */
2402 #define ISP_MAIN_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2403 #define ISP_MAIN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2404 #define SC_ISP_MAIN_PWR_ACK_LSB BIT(30) /* 1b */
2405 #define SC_ISP_MAIN_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2407 #define ISP_DIP1_PWR_RST_B_LSB BIT(0) /* 1b */
2408 #define ISP_DIP1_PWR_ISO_LSB BIT(1) /* 1b */
2409 #define ISP_DIP1_PWR_ON_LSB BIT(2) /* 1b */
2410 #define ISP_DIP1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2411 #define ISP_DIP1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2412 #define ISP_DIP1_SRAM_PDN_LSB BIT(8) /* 1b */
2413 #define SC_ISP_DIP1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2414 #define ISP_DIP1_RTFF_SAVE_LSB BIT(24) /* 1b */
2415 #define ISP_DIP1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2416 #define ISP_DIP1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2417 #define SC_ISP_DIP1_PWR_ACK_LSB BIT(30) /* 1b */
2418 #define SC_ISP_DIP1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2420 #define ISP_IPE_PWR_RST_B_LSB BIT(0) /* 1b */
2421 #define ISP_IPE_PWR_ISO_LSB BIT(1) /* 1b */
2422 #define ISP_IPE_PWR_ON_LSB BIT(2) /* 1b */
2423 #define ISP_IPE_PWR_ON_2ND_LSB BIT(3) /* 1b */
2424 #define ISP_IPE_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2425 #define ISP_IPE_SRAM_PDN_LSB BIT(8) /* 1b */
2426 #define SC_ISP_IPE_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2427 #define ISP_IPE_RTFF_SAVE_LSB BIT(24) /* 1b */
2428 #define ISP_IPE_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2429 #define ISP_IPE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2430 #define SC_ISP_IPE_PWR_ACK_LSB BIT(30) /* 1b */
2431 #define SC_ISP_IPE_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2433 #define ISP_VCORE_PWR_RST_B_LSB BIT(0) /* 1b */
2434 #define ISP_VCORE_PWR_ISO_LSB BIT(1) /* 1b */
2435 #define ISP_VCORE_PWR_ON_LSB BIT(2) /* 1b */
2436 #define ISP_VCORE_PWR_ON_2ND_LSB BIT(3) /* 1b */
2437 #define ISP_VCORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2438 #define ISP_VCORE_RTFF_SAVE_LSB BIT(24) /* 1b */
2439 #define ISP_VCORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2440 #define ISP_VCORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2441 #define SC_ISP_VCORE_PWR_ACK_LSB BIT(30) /* 1b */
2442 #define SC_ISP_VCORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2444 #define VDE0_PWR_RST_B_LSB BIT(0) /* 1b */
2445 #define VDE0_PWR_ISO_LSB BIT(1) /* 1b */
2446 #define VDE0_PWR_ON_LSB BIT(2) /* 1b */
2447 #define VDE0_PWR_ON_2ND_LSB BIT(3) /* 1b */
2448 #define VDE0_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2449 #define VDE0_SRAM_PDN_LSB BIT(8) /* 1b */
2450 #define SC_VDE0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2451 #define VDE0_RTFF_SAVE_LSB BIT(24) /* 1b */
2452 #define VDE0_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2453 #define VDE0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2454 #define SC_VDE0_PWR_ACK_LSB BIT(30) /* 1b */
2455 #define SC_VDE0_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2457 #define VDE1_PWR_RST_B_LSB BIT(0) /* 1b */
2458 #define VDE1_PWR_ISO_LSB BIT(1) /* 1b */
2459 #define VDE1_PWR_ON_LSB BIT(2) /* 1b */
2460 #define VDE1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2461 #define VDE1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2462 #define VDE1_SRAM_PDN_LSB BIT(8) /* 1b */
2463 #define SC_VDE1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2464 #define VDE1_RTFF_SAVE_LSB BIT(24) /* 1b */
2465 #define VDE1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2466 #define VDE1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2467 #define SC_VDE1_PWR_ACK_LSB BIT(30) /* 1b */
2468 #define SC_VDE1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2470 #define VEN0_PWR_RST_B_LSB BIT(0) /* 1b */
2471 #define VEN0_PWR_ISO_LSB BIT(1) /* 1b */
2472 #define VEN0_PWR_ON_LSB BIT(2) /* 1b */
2473 #define VEN0_PWR_ON_2ND_LSB BIT(3) /* 1b */
2474 #define VEN0_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2475 #define VEN0_SRAM_PDN_LSB BIT(8) /* 1b */
2476 #define SC_VEN0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2477 #define VEN0_RTFF_SAVE_LSB BIT(24) /* 1b */
2478 #define VEN0_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2479 #define VEN0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2480 #define SC_VEN0_PWR_ACK_LSB BIT(30) /* 1b */
2481 #define SC_VEN0_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2483 #define VEN1_PWR_RST_B_LSB BIT(0) /* 1b */
2484 #define VEN1_PWR_ISO_LSB BIT(1) /* 1b */
2485 #define VEN1_PWR_ON_LSB BIT(2) /* 1b */
2486 #define VEN1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2487 #define VEN1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2488 #define VEN1_SRAM_PDN_LSB BIT(8) /* 1b */
2489 #define SC_VEN1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2490 #define VEN1_RTFF_SAVE_LSB BIT(24) /* 1b */
2491 #define VEN1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2492 #define VEN1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2493 #define SC_VEN1_PWR_ACK_LSB BIT(30) /* 1b */
2494 #define SC_VEN1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2496 #define CAM_MAIN_PWR_RST_B_LSB BIT(0) /* 1b */
2497 #define CAM_MAIN_PWR_ISO_LSB BIT(1) /* 1b */
2498 #define CAM_MAIN_PWR_ON_LSB BIT(2) /* 1b */
2499 #define CAM_MAIN_PWR_ON_2ND_LSB BIT(3) /* 1b */
2500 #define CAM_MAIN_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2501 #define CAM_MAIN_SRAM_PDN_LSB BIT(8) /* 1b */
2502 #define SC_CAM_MAIN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2503 #define CAM_MAIN_RTFF_SAVE_LSB BIT(24) /* 1b */
2504 #define CAM_MAIN_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2505 #define CAM_MAIN_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2506 #define SC_CAM_MAIN_PWR_ACK_LSB BIT(30) /* 1b */
2507 #define SC_CAM_MAIN_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2509 #define CAM_MRAW_PWR_RST_B_LSB BIT(0) /* 1b */
2510 #define CAM_MRAW_PWR_ISO_LSB BIT(1) /* 1b */
2511 #define CAM_MRAW_PWR_ON_LSB BIT(2) /* 1b */
2512 #define CAM_MRAW_PWR_ON_2ND_LSB BIT(3) /* 1b */
2513 #define CAM_MRAW_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2514 #define CAM_MRAW_SRAM_PDN_LSB BIT(8) /* 1b */
2515 #define SC_CAM_MRAW_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2516 #define CAM_MRAW_RTFF_SAVE_LSB BIT(24) /* 1b */
2517 #define CAM_MRAW_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2518 #define CAM_MRAW_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2519 #define SC_CAM_MRAW_PWR_ACK_LSB BIT(30) /* 1b */
2520 #define SC_CAM_MRAW_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2522 #define CAM_SUBA_PWR_RST_B_LSB BIT(0) /* 1b */
2523 #define CAM_SUBA_PWR_ISO_LSB BIT(1) /* 1b */
2524 #define CAM_SUBA_PWR_ON_LSB BIT(2) /* 1b */
2525 #define CAM_SUBA_PWR_ON_2ND_LSB BIT(3) /* 1b */
2526 #define CAM_SUBA_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2527 #define CAM_SUBA_SRAM_PDN_LSB BIT(8) /* 1b */
2528 #define SC_CAM_SUBA_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2529 #define CAM_SUBA_RTFF_SAVE_LSB BIT(24) /* 1b */
2530 #define CAM_SUBA_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2531 #define CAM_SUBA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2532 #define SC_CAM_SUBA_PWR_ACK_LSB BIT(30) /* 1b */
2533 #define SC_CAM_SUBA_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2535 #define CAM_SUBB_PWR_RST_B_LSB BIT(0) /* 1b */
2536 #define CAM_SUBB_PWR_ISO_LSB BIT(1) /* 1b */
2537 #define CAM_SUBB_PWR_ON_LSB BIT(2) /* 1b */
2538 #define CAM_SUBB_PWR_ON_2ND_LSB BIT(3) /* 1b */
2539 #define CAM_SUBB_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2540 #define CAM_SUBB_SRAM_PDN_LSB BIT(8) /* 1b */
2541 #define SC_CAM_SUBB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2542 #define CAM_SUBB_RTFF_SAVE_LSB BIT(24) /* 1b */
2543 #define CAM_SUBB_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2544 #define CAM_SUBB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2545 #define SC_CAM_SUBB_PWR_ACK_LSB BIT(30) /* 1b */
2546 #define SC_CAM_SUBB_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2548 #define CAM_SUBC_PWR_RST_B_LSB BIT(0) /* 1b */
2549 #define CAM_SUBC_PWR_ISO_LSB BIT(1) /* 1b */
2550 #define CAM_SUBC_PWR_ON_LSB BIT(2) /* 1b */
2551 #define CAM_SUBC_PWR_ON_2ND_LSB BIT(3) /* 1b */
2552 #define CAM_SUBC_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2553 #define CAM_SUBC_SRAM_PDN_LSB BIT(8) /* 1b */
2554 #define SC_CAM_SUBC_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2555 #define CAM_SUBC_RTFF_SAVE_LSB BIT(24) /* 1b */
2556 #define CAM_SUBC_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2557 #define CAM_SUBC_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2558 #define SC_CAM_SUBC_PWR_ACK_LSB BIT(30) /* 1b */
2559 #define SC_CAM_SUBC_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2561 #define CAM_VCORE_PWR_RST_B_LSB BIT(0) /* 1b */
2562 #define CAM_VCORE_PWR_ISO_LSB BIT(1) /* 1b */
2563 #define CAM_VCORE_PWR_ON_LSB BIT(2) /* 1b */
2564 #define CAM_VCORE_PWR_ON_2ND_LSB BIT(3) /* 1b */
2565 #define CAM_VCORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2566 #define CAM_VCORE_RTFF_SAVE_LSB BIT(24) /* 1b */
2567 #define CAM_VCORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2568 #define CAM_VCORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2569 #define SC_CAM_VCORE_PWR_ACK_LSB BIT(30) /* 1b */
2570 #define SC_CAM_VCORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2572 #define CAM_CCU_PWR_RST_B_LSB BIT(0) /* 1b */
2573 #define CAM_CCU_PWR_ISO_LSB BIT(1) /* 1b */
2574 #define CAM_CCU_PWR_ON_LSB BIT(2) /* 1b */
2575 #define CAM_CCU_PWR_ON_2ND_LSB BIT(3) /* 1b */
2576 #define CAM_CCU_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2577 #define CAM_CCU_SRAM_PDN_LSB BIT(8) /* 1b */
2578 #define SC_CAM_CCU_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2579 #define CAM_CCU_RTFF_SAVE_LSB BIT(24) /* 1b */
2580 #define CAM_CCU_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2581 #define CAM_CCU_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2582 #define SC_CAM_CCU_PWR_ACK_LSB BIT(30) /* 1b */
2583 #define SC_CAM_CCU_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2585 #define CAM_CCU_AO_PWR_RST_B_LSB BIT(0) /* 1b */
2586 #define CAM_CCU_AO_PWR_ISO_LSB BIT(1) /* 1b */
2587 #define CAM_CCU_AO_PWR_ON_LSB BIT(2) /* 1b */
2588 #define CAM_CCU_AO_PWR_ON_2ND_LSB BIT(3) /* 1b */
2589 #define CAM_CCU_AO_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2590 #define CAM_CCU_AO_SRAM_CKISO_LSB BIT(5) /* 1b */
2591 #define CAM_CCU_AO_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2592 #define CAM_CCU_AO_SRAM_PDN_LSB BIT(8) /* 1b */
2593 #define CAM_CCU_AO_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2594 #define SC_CAM_CCU_AO_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2595 #define SC_CAM_CCU_AO_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2596 #define CAM_CCU_AO_RTFF_SAVE_LSB BIT(24) /* 1b */
2597 #define CAM_CCU_AO_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2598 #define CAM_CCU_AO_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2599 #define SC_CAM_CCU_AO_PWR_ACK_LSB BIT(30) /* 1b */
2600 #define SC_CAM_CCU_AO_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2602 #define MDP0_PWR_RST_B_LSB BIT(0) /* 1b */
2603 #define MDP0_PWR_ISO_LSB BIT(1) /* 1b */
2604 #define MDP0_PWR_ON_LSB BIT(2) /* 1b */
2605 #define MDP0_PWR_ON_2ND_LSB BIT(3) /* 1b */
2606 #define MDP0_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2607 #define MDP0_SRAM_PDN_LSB BIT(8) /* 1b */
2608 #define SC_MDP0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2609 #define MDP0_RTFF_SAVE_LSB BIT(24) /* 1b */
2610 #define MDP0_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2611 #define MDP0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2612 #define SC_MDP0_PWR_ACK_LSB BIT(30) /* 1b */
2613 #define SC_MDP0_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2615 #define MDP1_PWR_RST_B_LSB BIT(0) /* 1b */
2616 #define MDP1_PWR_ISO_LSB BIT(1) /* 1b */
2617 #define MDP1_PWR_ON_LSB BIT(2) /* 1b */
2618 #define MDP1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2619 #define MDP1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2620 #define MDP1_SRAM_PDN_LSB BIT(8) /* 1b */
2621 #define SC_MDP1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2622 #define MDP1_RTFF_SAVE_LSB BIT(24) /* 1b */
2623 #define MDP1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2624 #define MDP1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2625 #define SC_MDP1_PWR_ACK_LSB BIT(30) /* 1b */
2626 #define SC_MDP1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2628 #define DIS0_PWR_RST_B_LSB BIT(0) /* 1b */
2629 #define DIS0_PWR_ISO_LSB BIT(1) /* 1b */
2630 #define DIS0_PWR_ON_LSB BIT(2) /* 1b */
2631 #define DIS0_PWR_ON_2ND_LSB BIT(3) /* 1b */
2632 #define DIS0_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2633 #define DIS0_SRAM_CKISO_LSB BIT(5) /* 1b */
2634 #define DIS0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2635 #define DIS0_SRAM_PDN_LSB BIT(8) /* 1b */
2636 #define DIS0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2637 #define SC_DIS0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2638 #define SC_DIS0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2639 #define DIS0_RTFF_SAVE_LSB BIT(24) /* 1b */
2640 #define DIS0_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2641 #define DIS0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2642 #define SC_DIS0_PWR_ACK_LSB BIT(30) /* 1b */
2643 #define SC_DIS0_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2645 #define DIS1_PWR_RST_B_LSB BIT(0) /* 1b */
2646 #define DIS1_PWR_ISO_LSB BIT(1) /* 1b */
2647 #define DIS1_PWR_ON_LSB BIT(2) /* 1b */
2648 #define DIS1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2649 #define DIS1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2650 #define DIS1_SRAM_PDN_LSB BIT(8) /* 1b */
2651 #define SC_DIS1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2652 #define DIS1_RTFF_SAVE_LSB BIT(24) /* 1b */
2653 #define DIS1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2654 #define DIS1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2655 #define SC_DIS1_PWR_ACK_LSB BIT(30) /* 1b */
2656 #define SC_DIS1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2658 #define MM_INFRA_PWR_RST_B_LSB BIT(0) /* 1b */
2659 #define MM_INFRA_PWR_ISO_LSB BIT(1) /* 1b */
2660 #define MM_INFRA_PWR_ON_LSB BIT(2) /* 1b */
2661 #define MM_INFRA_PWR_ON_2ND_LSB BIT(3) /* 1b */
2662 #define MM_INFRA_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2663 #define MM_INFRA_SRAM_CKISO_LSB BIT(5) /* 1b */
2664 #define MM_INFRA_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2665 #define MM_INFRA_SRAM_PDN_LSB BIT(8) /* 1b */
2666 #define MM_INFRA_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2667 #define SC_MM_INFRA_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2668 #define SC_MM_INFRA_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2669 #define MM_INFRA_RTFF_SAVE_LSB BIT(24) /* 1b */
2670 #define MM_INFRA_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2671 #define MM_INFRA_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2672 #define SC_MM_INFRA_PWR_ACK_LSB BIT(30) /* 1b */
2673 #define SC_MM_INFRA_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2675 #define MM_PROC_PWR_RST_B_LSB BIT(0) /* 1b */
2676 #define MM_PROC_PWR_ISO_LSB BIT(1) /* 1b */
2677 #define MM_PROC_PWR_ON_LSB BIT(2) /* 1b */
2678 #define MM_PROC_PWR_ON_2ND_LSB BIT(3) /* 1b */
2679 #define MM_PROC_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2680 #define MM_PROC_SRAM_CKISO_LSB BIT(5) /* 1b */
2681 #define MM_PROC_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2682 #define MM_PROC_SRAM_PDN_LSB BIT(8) /* 1b */
2683 #define MM_PROC_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2684 #define SC_MM_PROC_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2685 #define SC_MM_PROC_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2686 #define MM_PROC_RTFF_SAVE_LSB BIT(24) /* 1b */
2687 #define MM_PROC_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2688 #define MM_PROC_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2689 #define SC_MM_PROC_PWR_ACK_LSB BIT(30) /* 1b */
2690 #define SC_MM_PROC_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2692 #define DP_TX_PWR_RST_B_LSB BIT(0) /* 1b */
2693 #define DP_TX_PWR_ISO_LSB BIT(1) /* 1b */
2694 #define DP_TX_PWR_ON_LSB BIT(2) /* 1b */
2695 #define DP_TX_PWR_ON_2ND_LSB BIT(3) /* 1b */
2696 #define DP_TX_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2697 #define DP_TX_SRAM_PDN_LSB BIT(8) /* 1b */
2698 #define SC_DP_TX_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2699 #define DP_TX_RTFF_SAVE_LSB BIT(24) /* 1b */
2700 #define DP_TX_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2701 #define DP_TX_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2702 #define SC_DP_TX_PWR_ACK_LSB BIT(30) /* 1b */
2703 #define SC_DP_TX_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2705 #define SCP_CORE_PWR_RST_B_LSB BIT(0) /* 1b */
2706 #define SCP_CORE_PWR_ISO_LSB BIT(1) /* 1b */
2707 #define SCP_CORE_PWR_ON_LSB BIT(2) /* 1b */
2708 #define SCP_CORE_PWR_ON_2ND_LSB BIT(3) /* 1b */
2709 #define SCP_CORE_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2710 #define SCP_CORE_SRAM_CKISO_LSB BIT(5) /* 1b */
2711 #define SCP_CORE_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2712 #define SCP_CORE_SRAM_PDN_LSB BIT(8) /* 1b */
2713 #define SCP_CORE_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2714 #define SC_SCP_CORE_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2715 #define SC_SCP_CORE_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2716 #define SCP_CORE_RTFF_SAVE_LSB BIT(24) /* 1b */
2717 #define SCP_CORE_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2718 #define SCP_CORE_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2719 #define SC_SCP_CORE_PWR_ACK_LSB BIT(30) /* 1b */
2720 #define SC_SCP_CORE_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2722 #define SCP_PERI_PWR_RST_B_LSB BIT(0) /* 1b */
2723 #define SCP_PERI_PWR_ISO_LSB BIT(1) /* 1b */
2724 #define SCP_PERI_PWR_ON_LSB BIT(2) /* 1b */
2725 #define SCP_PERI_PWR_ON_2ND_LSB BIT(3) /* 1b */
2726 #define SCP_PERI_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2727 #define SCP_PERI_SRAM_CKISO_LSB BIT(5) /* 1b */
2728 #define SCP_PERI_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2729 #define SCP_PERI_SRAM_PDN_LSB BIT(8) /* 1b */
2730 #define SCP_PERI_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2731 #define SC_SCP_PERI_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2732 #define SC_SCP_PERI_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2733 #define SCP_PERI_RTFF_SAVE_LSB BIT(24) /* 1b */
2734 #define SCP_PERI_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2735 #define SCP_PERI_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2736 #define SC_SCP_PERI_PWR_ACK_LSB BIT(30) /* 1b */
2737 #define SC_SCP_PERI_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2739 #define DPM0_PWR_RST_B_LSB BIT(0) /* 1b */
2740 #define DPM0_PWR_ISO_LSB BIT(1) /* 1b */
2741 #define DPM0_PWR_ON_LSB BIT(2) /* 1b */
2742 #define DPM0_PWR_ON_2ND_LSB BIT(3) /* 1b */
2743 #define DPM0_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2744 #define DPM0_SRAM_CKISO_LSB BIT(5) /* 1b */
2745 #define DPM0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2746 #define DPM0_SRAM_PDN_LSB BIT(8) /* 1b */
2747 #define DPM0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2748 #define SC_DPM0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2749 #define SC_DPM0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2750 #define DPM0_RTFF_SAVE_LSB BIT(24) /* 1b */
2751 #define DPM0_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2752 #define DPM0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2753 #define SC_DPM0_PWR_ACK_LSB BIT(30) /* 1b */
2754 #define SC_DPM0_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2756 #define DPM1_PWR_RST_B_LSB BIT(0) /* 1b */
2757 #define DPM1_PWR_ISO_LSB BIT(1) /* 1b */
2758 #define DPM1_PWR_ON_LSB BIT(2) /* 1b */
2759 #define DPM1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2760 #define DPM1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2761 #define DPM1_SRAM_CKISO_LSB BIT(5) /* 1b */
2762 #define DPM1_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2763 #define DPM1_SRAM_PDN_LSB BIT(8) /* 1b */
2764 #define DPM1_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2765 #define SC_DPM1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2766 #define SC_DPM1_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2767 #define DPM1_RTFF_SAVE_LSB BIT(24) /* 1b */
2768 #define DPM1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2769 #define DPM1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2770 #define SC_DPM1_PWR_ACK_LSB BIT(30) /* 1b */
2771 #define SC_DPM1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2773 #define EMI0_PWR_RST_B_LSB BIT(0) /* 1b */
2774 #define EMI0_PWR_ISO_LSB BIT(1) /* 1b */
2775 #define EMI0_PWR_ON_LSB BIT(2) /* 1b */
2776 #define EMI0_PWR_ON_2ND_LSB BIT(3) /* 1b */
2777 #define EMI0_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2778 #define EMI0_SRAM_CKISO_LSB BIT(5) /* 1b */
2779 #define EMI0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2780 #define EMI0_SRAM_PDN_LSB BIT(8) /* 1b */
2781 #define EMI0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2782 #define SC_EMI0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2783 #define SC_EMI0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2784 #define EMI0_RTFF_SAVE_LSB BIT(24) /* 1b */
2785 #define EMI0_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2786 #define EMI0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2787 #define SC_EMI0_PWR_ACK_LSB BIT(30) /* 1b */
2788 #define SC_EMI0_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2790 #define EMI1_PWR_RST_B_LSB BIT(0) /* 1b */
2791 #define EMI1_PWR_ISO_LSB BIT(1) /* 1b */
2792 #define EMI1_PWR_ON_LSB BIT(2) /* 1b */
2793 #define EMI1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2794 #define EMI1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2795 #define EMI1_SRAM_CKISO_LSB BIT(5) /* 1b */
2796 #define EMI1_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2797 #define EMI1_SRAM_PDN_LSB BIT(8) /* 1b */
2798 #define EMI1_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2799 #define SC_EMI1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2800 #define SC_EMI1_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2801 #define EMI1_RTFF_SAVE_LSB BIT(24) /* 1b */
2802 #define EMI1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2803 #define EMI1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2804 #define SC_EMI1_PWR_ACK_LSB BIT(30) /* 1b */
2805 #define SC_EMI1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2807 #define CSI_RX_PWR_RST_B_LSB BIT(0) /* 1b */
2808 #define CSI_RX_PWR_ISO_LSB BIT(1) /* 1b */
2809 #define CSI_RX_PWR_ON_LSB BIT(2) /* 1b */
2810 #define CSI_RX_PWR_ON_2ND_LSB BIT(3) /* 1b */
2811 #define CSI_RX_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2812 #define CSI_RX_SRAM_PDN_LSB BIT(8) /* 1b */
2813 #define SC_CSI_RX_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2814 #define CSI_RX_RTFF_SAVE_LSB BIT(24) /* 1b */
2815 #define CSI_RX_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2816 #define CSI_RX_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2817 #define SC_CSI_RX_PWR_ACK_LSB BIT(30) /* 1b */
2818 #define SC_CSI_RX_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2820 #define SSRSYS_PWR_RST_B_LSB BIT(0) /* 1b */
2821 #define SSRSYS_PWR_ISO_LSB BIT(1) /* 1b */
2822 #define SSRSYS_PWR_ON_LSB BIT(2) /* 1b */
2823 #define SSRSYS_PWR_ON_2ND_LSB BIT(3) /* 1b */
2824 #define SSRSYS_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2825 #define SSRSYS_SRAM_CKISO_LSB BIT(5) /* 1b */
2826 #define SSRSYS_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2827 #define SSRSYS_SRAM_PDN_LSB BIT(8) /* 1b */
2828 #define SSRSYS_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2829 #define SC_SSRSYS_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2830 #define SC_SSRSYS_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2831 #define SSRSYS_RTFF_SAVE_LSB BIT(24) /* 1b */
2832 #define SSRSYS_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2833 #define SSRSYS_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2834 #define SC_SSRSYS_PWR_ACK_LSB BIT(30) /* 1b */
2835 #define SC_SSRSYS_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2837 #define SSPM_PWR_RST_B_LSB BIT(0) /* 1b */
2838 #define SSPM_PWR_ISO_LSB BIT(1) /* 1b */
2839 #define SSPM_PWR_ON_LSB BIT(2) /* 1b */
2840 #define SSPM_PWR_ON_2ND_LSB BIT(3) /* 1b */
2841 #define SSPM_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2842 #define SSPM_RTFF_SAVE_LSB BIT(24) /* 1b */
2843 #define SSPM_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2844 #define SSPM_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2845 #define SC_SSPM_PWR_ACK_LSB BIT(30) /* 1b */
2846 #define SC_SSPM_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2848 #define SSUSB_PWR_RST_B_LSB BIT(0) /* 1b */
2849 #define SSUSB_PWR_ISO_LSB BIT(1) /* 1b */
2850 #define SSUSB_PWR_ON_LSB BIT(2) /* 1b */
2851 #define SSUSB_PWR_ON_2ND_LSB BIT(3) /* 1b */
2852 #define SSUSB_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2853 #define SSUSB_SRAM_PDN_LSB BIT(8) /* 1b */
2854 #define SC_SSUSB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2855 #define SSUSB_RTFF_SAVE_LSB BIT(24) /* 1b */
2856 #define SSUSB_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2857 #define SSUSB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2858 #define SC_SSUSB_PWR_ACK_LSB BIT(30) /* 1b */
2859 #define SC_SSUSB_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2861 #define SSUSB_PHY_PWR_RST_B_LSB BIT(0) /* 1b */
2862 #define SSUSB_PHY_PWR_ISO_LSB BIT(1) /* 1b */
2863 #define SSUSB_PHY_PWR_ON_LSB BIT(2) /* 1b */
2864 #define SSUSB_PHY_PWR_ON_2ND_LSB BIT(3) /* 1b */
2865 #define SSUSB_PHY_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2866 #define SSUSB_PHY_RTFF_SAVE_LSB BIT(24) /* 1b */
2867 #define SSUSB_PHY_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2868 #define SSUSB_PHY_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2869 #define SC_SSUSB_PHY_PWR_ACK_LSB BIT(30) /* 1b */
2870 #define SC_SSUSB_PHY_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2872 #define CPUEB_PWR_RST_B_LSB BIT(0) /* 1b */
2873 #define CPUEB_PWR_ISO_LSB BIT(1) /* 1b */
2874 #define CPUEB_PWR_ON_LSB BIT(2) /* 1b */
2875 #define CPUEB_PWR_ON_2ND_LSB BIT(3) /* 1b */
2876 #define CPUEB_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2877 #define CPUEB_SRAM_CKISO_LSB BIT(5) /* 1b */
2878 #define CPUEB_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2879 #define CPUEB_SRAM_PDN_LSB BIT(8) /* 1b */
2880 #define CPUEB_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2881 #define SC_CPUEB_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2882 #define SC_CPUEB_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2883 #define CPUEB_RTFF_SAVE_LSB BIT(24) /* 1b */
2884 #define CPUEB_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2885 #define CPUEB_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2886 #define SC_CPUEB_PWR_ACK_LSB BIT(30) /* 1b */
2887 #define SC_CPUEB_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2889 #define MFG0_PWR_RST_B_LSB BIT(0) /* 1b */
2890 #define MFG0_PWR_ISO_LSB BIT(1) /* 1b */
2891 #define MFG0_PWR_ON_LSB BIT(2) /* 1b */
2892 #define MFG0_PWR_ON_2ND_LSB BIT(3) /* 1b */
2893 #define MFG0_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2894 #define MFG0_SRAM_CKISO_LSB BIT(5) /* 1b */
2895 #define MFG0_SRAM_ISOINT_B_LSB BIT(6) /* 1b */
2896 #define MFG0_SRAM_PDN_LSB BIT(8) /* 1b */
2897 #define MFG0_SRAM_SLEEP_B_LSB BIT(9) /* 1b */
2898 #define SC_MFG0_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2899 #define SC_MFG0_SRAM_SLEEP_B_ACK_LSB BIT(13) /* 1b */
2900 #define MFG0_RTFF_SAVE_LSB BIT(24) /* 1b */
2901 #define MFG0_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2902 #define MFG0_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2903 #define SC_MFG0_PWR_ACK_LSB BIT(30) /* 1b */
2904 #define SC_MFG0_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2906 #define MFG1_PWR_RST_B_LSB BIT(0) /* 1b */
2907 #define MFG1_PWR_ISO_LSB BIT(1) /* 1b */
2908 #define MFG1_PWR_ON_LSB BIT(2) /* 1b */
2909 #define MFG1_PWR_ON_2ND_LSB BIT(3) /* 1b */
2910 #define MFG1_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2911 #define MFG1_SRAM_PDN_LSB BIT(8) /* 1b */
2912 #define SC_MFG1_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2913 #define MFG1_RTFF_SAVE_LSB BIT(24) /* 1b */
2914 #define MFG1_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2915 #define MFG1_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2916 #define SC_MFG1_PWR_ACK_LSB BIT(30) /* 1b */
2917 #define SC_MFG1_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2919 #define MFG2_PWR_RST_B_LSB BIT(0) /* 1b */
2920 #define MFG2_PWR_ISO_LSB BIT(1) /* 1b */
2921 #define MFG2_PWR_ON_LSB BIT(2) /* 1b */
2922 #define MFG2_PWR_ON_2ND_LSB BIT(3) /* 1b */
2923 #define MFG2_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2924 #define MFG2_SRAM_PDN_LSB BIT(8) /* 1b */
2925 #define SC_MFG2_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2926 #define MFG2_RTFF_SAVE_LSB BIT(24) /* 1b */
2927 #define MFG2_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2928 #define MFG2_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2929 #define SC_MFG2_PWR_ACK_LSB BIT(30) /* 1b */
2930 #define SC_MFG2_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2932 #define MFG3_PWR_RST_B_LSB BIT(0) /* 1b */
2933 #define MFG3_PWR_ISO_LSB BIT(1) /* 1b */
2934 #define MFG3_PWR_ON_LSB BIT(2) /* 1b */
2935 #define MFG3_PWR_ON_2ND_LSB BIT(3) /* 1b */
2936 #define MFG3_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2937 #define MFG3_SRAM_PDN_LSB BIT(8) /* 1b */
2938 #define SC_MFG3_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2939 #define MFG3_RTFF_SAVE_LSB BIT(24) /* 1b */
2940 #define MFG3_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2941 #define MFG3_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2942 #define SC_MFG3_PWR_ACK_LSB BIT(30) /* 1b */
2943 #define SC_MFG3_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2945 #define MFG4_PWR_RST_B_LSB BIT(0) /* 1b */
2946 #define MFG4_PWR_ISO_LSB BIT(1) /* 1b */
2947 #define MFG4_PWR_ON_LSB BIT(2) /* 1b */
2948 #define MFG4_PWR_ON_2ND_LSB BIT(3) /* 1b */
2949 #define MFG4_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2950 #define MFG4_SRAM_PDN_LSB BIT(8) /* 1b */
2951 #define SC_MFG4_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2952 #define MFG4_RTFF_SAVE_LSB BIT(24) /* 1b */
2953 #define MFG4_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2954 #define MFG4_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2955 #define SC_MFG4_PWR_ACK_LSB BIT(30) /* 1b */
2956 #define SC_MFG4_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2958 #define MFG5_PWR_RST_B_LSB BIT(0) /* 1b */
2959 #define MFG5_PWR_ISO_LSB BIT(1) /* 1b */
2960 #define MFG5_PWR_ON_LSB BIT(2) /* 1b */
2961 #define MFG5_PWR_ON_2ND_LSB BIT(3) /* 1b */
2962 #define MFG5_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2963 #define MFG5_SRAM_PDN_LSB BIT(8) /* 1b */
2964 #define SC_MFG5_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2965 #define MFG5_RTFF_SAVE_LSB BIT(24) /* 1b */
2966 #define MFG5_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2967 #define MFG5_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2968 #define SC_MFG5_PWR_ACK_LSB BIT(30) /* 1b */
2969 #define SC_MFG5_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2971 #define MFG6_PWR_RST_B_LSB BIT(0) /* 1b */
2972 #define MFG6_PWR_ISO_LSB BIT(1) /* 1b */
2973 #define MFG6_PWR_ON_LSB BIT(2) /* 1b */
2974 #define MFG6_PWR_ON_2ND_LSB BIT(3) /* 1b */
2975 #define MFG6_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2976 #define MFG6_SRAM_PDN_LSB BIT(8) /* 1b */
2977 #define SC_MFG6_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2978 #define MFG6_RTFF_SAVE_LSB BIT(24) /* 1b */
2979 #define MFG6_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2980 #define MFG6_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2981 #define SC_MFG6_PWR_ACK_LSB BIT(30) /* 1b */
2982 #define SC_MFG6_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2984 #define MFG7_PWR_RST_B_LSB BIT(0) /* 1b */
2985 #define MFG7_PWR_ISO_LSB BIT(1) /* 1b */
2986 #define MFG7_PWR_ON_LSB BIT(2) /* 1b */
2987 #define MFG7_PWR_ON_2ND_LSB BIT(3) /* 1b */
2988 #define MFG7_PWR_CLK_DIS_LSB BIT(4) /* 1b */
2989 #define MFG7_SRAM_PDN_LSB BIT(8) /* 1b */
2990 #define SC_MFG7_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
2991 #define MFG7_RTFF_SAVE_LSB BIT(24) /* 1b */
2992 #define MFG7_RTFF_NRESTORE_LSB BIT(25) /* 1b */
2993 #define MFG7_RTFF_CLK_DIS_LSB BIT(28) /* 1b */
2994 #define SC_MFG7_PWR_ACK_LSB BIT(30) /* 1b */
2995 #define SC_MFG7_PWR_ACK_2ND_LSB BIT(31) /* 1b */
2997 #define ADSP_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */
2998 #define ADSP_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
2999 #define ADSP_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 1b */
3000 #define ADSP_HRE_SRAM_PDN_LSB BIT(16) /* 1b */
3002 #define CCU_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */
3003 #define CCU_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
3004 #define CCU_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */
3005 #define CCU_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */
3006 #define SC_CCU_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */
3007 #define SC_CCU_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */
3009 #define EFUSE_SRAM_CKISO_LSB BIT(0) /* 1b */
3010 #define EFUSE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
3011 #define EFUSE_SRAM_SLEEP_B_LSB BIT(4) /* 1b */
3012 #define EFUSE_SRAM_PDN_LSB BIT(16) /* 1b */
3014 #define EMI_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */
3015 #define EMI_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
3016 #define EMI_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 8b */
3017 #define EMI_HRE_SRAM_PDN_LSB BIT(16) /* 8b */
3019 #define EMI_SLB_SRAM_PDN_LSB BIT(0) /* 12b */
3020 #define SC_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 12b */
3022 #define INFRA_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */
3023 #define INFRA_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 2b */
3024 #define INFRA_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 6b */
3025 #define INFRA_HRE_SRAM_PDN_LSB BIT(16) /* 6b */
3027 #define INFRA_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */
3028 #define INFRA_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 2b */
3029 #define INFRA_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 2b */
3030 #define INFRA_SLEEP_SRAM_PDN_LSB BIT(8) /* 2b */
3031 #define SC_INFRA_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 2b */
3032 #define SC_INFRA_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(18) /* 2b */
3034 #define MM_HRE_SRAM_CKISO_LSB BIT(0) /* 1b */
3035 #define MM_HRE_SRAM_ISOINT_B_LSB BIT(1) /* 3b */
3036 #define MM_HRE_SRAM_SLEEP_B_LSB BIT(4) /* 3b */
3037 #define MM_HRE_SRAM_PDN_LSB BIT(16) /* 3b */
3039 #define NTH_EMI_SLB_SRAM_SLEEP_B_LSB BIT(0) /* 16b */
3040 #define NTH_EMI_SLB_SRAM_PDN_LSB BIT(16) /* 16b */
3042 #define SC_NTH_EMI_SLB_SRAM_SLEEP_B_ACK_LSB BIT(0) /* 16b */
3043 #define SC_NTH_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 16b */
3045 #define PERI_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */
3046 #define PERI_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
3047 #define PERI_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */
3048 #define PERI_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */
3049 #define SC_PERI_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */
3050 #define SC_PERI_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */
3052 #define SPM_SRAM_CKISO_LSB BIT(0) /* 1b */
3053 #define REG_SPM_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
3054 #define REG_SPM_SRAM_SLEEP_B_LSB BIT(4) /* 4b */
3055 #define SPM_SRAM_PDN_LSB BIT(16) /* 4b */
3057 #define SSPM_SRAM_CKISO_LSB BIT(0) /* 1b */
3058 #define SSPM_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
3059 #define SSPM_SRAM_SLEEP_B_LSB BIT(4) /* 1b */
3060 #define SSPM_SRAM_PDN_LSB BIT(16) /* 1b */
3062 #define SSR_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */
3063 #define SSR_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
3064 #define SSR_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */
3065 #define SSR_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */
3066 #define SC_SSR_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */
3067 #define SC_SSR_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */
3069 #define STH_EMI_SLB_SRAM_SLEEP_B_LSB BIT(0) /* 16b */
3070 #define STH_EMI_SLB_SRAM_PDN_LSB BIT(16) /* 16b */
3072 #define SC_STH_EMI_SLB_SRAM_SLEEP_B_ACK_LSB BIT(0) /* 16b */
3073 #define SC_STH_EMI_SLB_SRAM_PDN_ACK_LSB BIT(16) /* 16b */
3075 #define UFS_PDN_SRAM_PDN_LSB BIT(0) /* 1b */
3076 #define SC_UFS_PDN_SRAM_PDN_ACK_LSB BIT(12) /* 1b */
3078 #define UFS_SLEEP_SRAM_CKISO_LSB BIT(0) /* 1b */
3079 #define UFS_SLEEP_SRAM_ISOINT_B_LSB BIT(1) /* 1b */
3080 #define UFS_SLEEP_SRAM_SLEEP_B_LSB BIT(4) /* 1b */
3081 #define UFS_SLEEP_SRAM_PDN_LSB BIT(8) /* 1b */
3082 #define SC_UFS_SLEEP_SRAM_PDN_ACK_LSB BIT(16) /* 1b */
3083 #define SC_UFS_SLEEP_SRAM_SLEEP_B_ACK_LSB BIT(17) /* 1b */
3085 #define UNIPRO_PDN_SRAM_PDN_LSB BIT(0) /* 1b */
3086 #define SC_UNIPRO_PDN_SRAM_PDN_ACK_LSB BIT(8) /* 1b */
3088 #define MCUSYS_VPROC_EXT_OFF_LSB BIT(0) /* 1b */
3089 #define MP0_VPROC_EXT_OFF_LSB BIT(1) /* 1b */
3090 #define MP0_VPROC_EXT_OFF_CPU0_LSB BIT(2) /* 1b */
3091 #define MP0_VPROC_EXT_OFF_CPU1_LSB BIT(3) /* 1b */
3092 #define MP0_VPROC_EXT_OFF_CPU2_LSB BIT(4) /* 1b */
3093 #define MP0_VPROC_EXT_OFF_CPU3_LSB BIT(5) /* 1b */
3094 #define MP0_VPROC_EXT_OFF_CPU4_LSB BIT(6) /* 1b */
3095 #define MP0_VPROC_EXT_OFF_CPU5_LSB BIT(7) /* 1b */
3096 #define MP0_VPROC_EXT_OFF_CPU6_LSB BIT(8) /* 1b */
3097 #define MP0_VPROC_EXT_OFF_CPU7_LSB BIT(9) /* 1b */
3098 #define MP0_VSRAM_EXT_OFF_LSB BIT(10) /* 1b */
3100 #define VMD_EXT_BUCK_ISO_LSB BIT(0) /* 1b */
3101 #define AOC_VMD_SRAM_ISO_DIN_LSB BIT(1) /* 1b */
3102 #define AOC_VMD_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */
3103 #define AOC_VMD_ANA_ISO_LSB BIT(3) /* 1b */
3104 #define VMODEM_EXT_BUCK_ISO_LSB BIT(4) /* 1b */
3105 #define AOC_VMODEM_SRAM_ISO_DIN_LSB BIT(5) /* 1b */
3106 #define AOC_VMODEM_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */
3107 #define AOC_VMODEM_ANA_ISO_LSB BIT(7) /* 1b */
3109 #define SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */
3110 #define AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */
3111 #define AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */
3112 #define AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */
3113 #define VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */
3114 #define AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */
3115 #define AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */
3116 #define AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */
3117 #define VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */
3118 #define AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */
3119 #define AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */
3120 #define AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */
3121 #define VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */
3122 #define AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */
3123 #define AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */
3124 #define AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */
3125 #define VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */
3126 #define AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */
3127 #define AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */
3128 #define AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */
3129 #define VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */
3130 #define AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */
3131 #define AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */
3132 #define AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */
3133 #define VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */
3134 #define AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */
3135 #define AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */
3136 #define AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */
3137 #define VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */
3138 #define AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */
3139 #define AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */
3140 #define AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */
3142 #define SOC_BUCK_ISO_CON_SET_SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */
3143 #define SOC_BUCK_ISO_CON_SET_AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */
3144 #define SOC_BUCK_ISO_CON_SET_AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */
3145 #define SOC_BUCK_ISO_CON_SET_AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */
3146 #define SOC_BUCK_ISO_CON_SET_VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */
3147 #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */
3148 #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */
3149 #define SOC_BUCK_ISO_CON_SET_AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */
3150 #define SOC_BUCK_ISO_CON_SET_VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */
3151 #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */
3152 #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */
3153 #define SOC_BUCK_ISO_CON_SET_AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */
3154 #define SOC_BUCK_ISO_CON_SET_VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */
3155 #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */
3156 #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */
3157 #define SOC_BUCK_ISO_CON_SET_AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */
3158 #define SOC_BUCK_ISO_CON_SET_VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */
3159 #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */
3160 #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */
3161 #define SOC_BUCK_ISO_CON_SET_AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */
3162 #define SOC_BUCK_ISO_CON_SET_VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */
3163 #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */
3164 #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */
3165 #define SOC_BUCK_ISO_CON_SET_AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */
3166 #define SOC_BUCK_ISO_CON_SET_VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */
3167 #define SOC_BUCK_ISO_CON_SET_AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */
3168 #define SOC_BUCK_ISO_CON_SET_AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */
3169 #define SOC_BUCK_ISO_CON_SET_AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */
3170 #define SOC_BUCK_ISO_CON_SET_VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */
3171 #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */
3172 #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */
3173 #define SOC_BUCK_ISO_CON_SET_AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */
3175 #define SOC_BUCK_ISO_CON_CLR_SCP_EXT_BUCK_ISO_LSB BIT(0) /* 1b */
3176 #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_SRAM_ISO_DIN_LSB BIT(1) /* 1b */
3177 #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */
3178 #define SOC_BUCK_ISO_CON_CLR_AOC_SCP_ANA_ISO_LSB BIT(3) /* 1b */
3179 #define SOC_BUCK_ISO_CON_CLR_VADSP_EXT_BUCK_ISO_LSB BIT(4) /* 1b */
3180 #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_SRAM_ISO_DIN_LSB BIT(5) /* 1b */
3181 #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */
3182 #define SOC_BUCK_ISO_CON_CLR_AOC_VADSP_ANA_ISO_LSB BIT(7) /* 1b */
3183 #define SOC_BUCK_ISO_CON_CLR_VAPU_EXT_BUCK_ISO_LSB BIT(8) /* 1b */
3184 #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_SRAM_ISO_DIN_LSB BIT(9) /* 1b */
3185 #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_SRAM_LATCH_ENB_LSB BIT(10) /* 1b */
3186 #define SOC_BUCK_ISO_CON_CLR_AOC_VAPU_ANA_ISO_LSB BIT(11) /* 1b */
3187 #define SOC_BUCK_ISO_CON_CLR_VDISP_EXT_BUCK_ISO_LSB BIT(12) /* 1b */
3188 #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_SRAM_ISO_DIN_LSB BIT(13) /* 1b */
3189 #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_SRAM_LATCH_ENB_LSB BIT(14) /* 1b */
3190 #define SOC_BUCK_ISO_CON_CLR_AOC_VDISP_ANA_ISO_LSB BIT(15) /* 1b */
3191 #define SOC_BUCK_ISO_CON_CLR_VGPU_EXT_BUCK_ISO_LSB BIT(16) /* 1b */
3192 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_SRAM_ISO_DIN_LSB BIT(17) /* 1b */
3193 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_SRAM_LATCH_ENB_LSB BIT(18) /* 1b */
3194 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPU_ANA_ISO_LSB BIT(19) /* 1b */
3195 #define SOC_BUCK_ISO_CON_CLR_VGPUTOP_EXT_BUCK_ISO_LSB BIT(20) /* 1b */
3196 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_SRAM_ISO_DIN_LSB BIT(21) /* 1b */
3197 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_SRAM_LATCH_ENB_LSB BIT(22) /* 1b */
3198 #define SOC_BUCK_ISO_CON_CLR_AOC_VGPUTOP_ANA_ISO_LSB BIT(23) /* 1b */
3199 #define SOC_BUCK_ISO_CON_CLR_VMM_EXT_BUCK_ISO_LSB BIT(24) /* 1b */
3200 #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_SRAM_ISO_DIN_LSB BIT(25) /* 1b */
3201 #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_SRAM_LATCH_ENB_LSB BIT(26) /* 1b */
3202 #define SOC_BUCK_ISO_CON_CLR_AOC_VMM_ANA_ISO_LSB BIT(27) /* 1b */
3203 #define SOC_BUCK_ISO_CON_CLR_VBSSR_EXT_BUCK_ISO_LSB BIT(28) /* 1b */
3204 #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_SRAM_ISO_DIN_LSB BIT(29) /* 1b */
3205 #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_SRAM_LATCH_ENB_LSB BIT(30) /* 1b */
3206 #define SOC_BUCK_ISO_CON_CLR_AOC_VBSSR_ANA_ISO_LSB BIT(31) /* 1b */
3208 #define VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */
3209 #define AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */
3210 #define AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */
3211 #define AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */
3212 #define VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */
3213 #define AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */
3214 #define AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */
3215 #define AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */
3217 #define SOC_BUCK_ISO_CON_2_SET_VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */
3218 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */
3219 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */
3220 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */
3221 #define SOC_BUCK_ISO_CON_2_SET_VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */
3222 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */
3223 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */
3224 #define SOC_BUCK_ISO_CON_2_SET_AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */
3226 #define SOC_BUCK_ISO_CON_2_CLR_VSTACK2_EXT_BUCK_ISO_LSB BIT(0) /* 1b */
3227 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_SRAM_ISO_DIN_LSB BIT(1) /* 1b */
3228 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_SRAM_LATCH_ENB_LSB BIT(2) /* 1b */
3229 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK2_ANA_ISO_LSB BIT(3) /* 1b */
3230 #define SOC_BUCK_ISO_CON_2_CLR_VSTACK_EXT_BUCK_ISO_LSB BIT(4) /* 1b */
3231 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_SRAM_ISO_DIN_LSB BIT(5) /* 1b */
3232 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_SRAM_LATCH_ENB_LSB BIT(6) /* 1b */
3233 #define SOC_BUCK_ISO_CON_2_CLR_AOC_VSTACK_ANA_ISO_LSB BIT(7) /* 1b */
3235 #define PWR_STATUS_LSB BIT(0) /* 32b */
3237 #define PWR_STATUS_2ND_LSB BIT(0) /* 32b */
3239 #define PWR_STATUS_MSB_LSB BIT(0) /* 32b */
3241 #define PWR_STATUS_MSB_2ND_LSB BIT(0) /* 32b */
3243 #define XPU_PWR_STATUS_LSB BIT(0) /* 32b */
3245 #define XPU_PWR_STATUS_2ND_LSB BIT(0) /* 32b */
3247 #define DFD_SOC_PWR_LATCH_LSB BIT(0) /* 32b */
3249 #define PM_BYPASS_MODE_LSB BIT(0) /* 16b */
3251 #define REG_TWAM_ENABLE_LSB BIT(0) /* 1b */
3252 #define REG_TWAM_SPEED_MODE_EN_LSB BIT(1) /* 1b */
3253 #define SPM_TWAM_EVENT_CLEAR_LSB BIT(2) /* 1b */
3254 #define REG_TWAM_IRQ_MASK_LSB BIT(3) /* 1b */
3255 #define REG_TWAM_MON_TYPE_0_LSB BIT(4) /* 2b */
3256 #define REG_TWAM_MON_TYPE_1_LSB BIT(6) /* 2b */
3257 #define REG_TWAM_MON_TYPE_2_LSB BIT(8) /* 2b */
3258 #define REG_TWAM_MON_TYPE_3_LSB BIT(10) /* 2b */
3259 #define REG_TWAM_IRQ_CLEAR_LSB BIT(16) /* 1b */
3260 #define TWAM_IRQ_LSB BIT(24) /* 1b */
3262 #define REG_TWAM_WINDOW_LEN_LSB BIT(0) /* 32b */
3264 #define REG_TWAM_SIG_SEL_0_LSB BIT(0) /* 7b */
3265 #define REG_TWAM_SIG_SEL_1_LSB BIT(8) /* 7b */
3266 #define REG_TWAM_SIG_SEL_2_LSB BIT(16) /* 7b */
3267 #define REG_TWAM_SIG_SEL_3_LSB BIT(24) /* 7b */
3269 #define TWAM_LAST_IDLE_CNT_0_LSB BIT(0) /* 32b */
3271 #define TWAM_LAST_IDLE_CNT_1_LSB BIT(0) /* 32b */
3273 #define TWAM_LAST_IDLE_CNT_2_LSB BIT(0) /* 32b */
3275 #define TWAM_LAST_IDLE_CNT_3_LSB BIT(0) /* 32b */
3277 #define TWAM_CURRENT_IDLE_CNT_0_LSB BIT(0) /* 32b */
3279 #define TWAM_CURRENT_IDLE_CNT_1_LSB BIT(0) /* 32b */
3281 #define TWAM_CURRENT_IDLE_CNT_2_LSB BIT(0) /* 32b */
3283 #define TWAM_CURRENT_IDLE_CNT_3_LSB BIT(0) /* 32b */
3285 #define TWAM_TIMER_LSB BIT(0) /* 32b */