Lines Matching refs:BIT
44 #define CTRL0_SC_26M_CK_OFF BIT(0)
45 #define CTRL0_SC_VLP_BUS_CK_OFF BIT(1)
46 #define CTRL0_SC_PMIF_CK_OFF BIT(2)
47 #define CTRL0_SC_AXI_CK_OFF BIT(3)
48 #define CTRL0_SC_AXI_MEM_CK_OFF BIT(4)
49 #define CTRL0_SC_MD26M_CK_OFF BIT(5)
50 #define CTRL0_SC_MD32K_CK_OFF BIT(6)
51 #define CTRL0_SC_VLP_26M_CLK_SEL BIT(7)
52 #define CTRL0_SC_26M_CK_SEL BIT(8)
53 #define CTRL0_SC_TOP_26M_CLK_SEL BIT(9)
54 #define CTRL0_SC_SYS_TIMER_CLK_32K_SEL BIT(10)
55 #define CTRL0_SC_CIRQ_CLK_32K_SEL BIT(11)
56 #define CTRL0_SC_AXI_DCM_DIS BIT(12)
57 #define CTRL0_SC_CKSQ0_OFF BIT(13)
58 #define CTRL0_SC_CKSQ1_OFF BIT(14)
59 #define CTRL0_VCORE_PWR_ISO BIT(15)
60 #define CTRL0_VCORE_PWR_ISO_PRE BIT(16)
61 #define CTRL0_VCORE_PWR_RST_B BIT(17)
62 #define CTRL0_VCORE_RESTORE_ENABLE BIT(18)
63 #define CTRL0_SC_TOP_RESTORE_26M_CLK_SEL BIT(19)
64 #define CTRL0_AOC_VCORE_SRAM_ISO_DIN BIT(20)
65 #define CTRL0_AOC_VCORE_SRAM_LATCH_ENB BIT(21)
66 #define CTRL0_AOC_VCORE_ANA_ISO BIT(22)
67 #define CTRL0_AOC_VCORE_ANA_ISO_PRE BIT(23)
68 #define CTRL0_AOC_VLPTOP_SRAM_ISO_DIN BIT(24)
69 #define CTRL0_AOC_VLPTOP_SRAM_LATCH_ENB BIT(25)
70 #define CTRL0_AOC_VCORE_IO_ISO BIT(26)
71 #define CTRL0_AOC_VCORE_IO_LATCH_ENB BIT(27)
72 #define CTRL0_RTFF_VCORE_SAVE BIT(28)
73 #define CTRL0_RTFF_VCORE_NRESTORE BIT(29)
74 #define CTRL0_RTFF_VCORE_CLK_DIS BIT(30)
77 #define CTRL1_PWRAP_SLEEP_REQ BIT(0)
78 #define CTRL1_IM_SLP_EN BIT(1)
79 #define CTRL1_SPM_LEAVE_VCORE_OFF_REQ BIT(2)
80 #define CTRL1_SPM_CK_SEL0 BIT(4)
81 #define CTRL1_SPM_CK_SEL1 BIT(5)
82 #define CTRL1_TIMER_SET BIT(6)
83 #define CTRL1_TIMER_CLR BIT(7)
84 #define CTRL1_SPM_LEAVE_DEEPIDLE_REQ BIT(8)
85 #define CTRL1_SPM_LEAVE_SUSPEND_REQ BIT(9)
86 #define CTRL1_CSYSPWRUPACK BIT(10)
87 #define CTRL1_SRCCLKENO0 BIT(11)
88 #define CTRL1_SRCCLKENO1 BIT(12)
89 #define CTRL1_SRCCLKENO2 BIT(13)
90 #define CTRL1_SPM_APSRC_INTERNAL_ACK BIT(14)
91 #define CTRL1_SPM_EMI_INTERNAL_ACK BIT(15)
92 #define CTRL1_SPM_DDREN_INTERNAL_ACK BIT(16)
93 #define CTRL1_SPM_INFRA_INTERNAL_ACK BIT(17)
94 #define CTRL1_SPM_VRF18_INTERNAL_ACK BIT(18)
95 #define CTRL1_SPM_VCORE_INTERNAL_ACK BIT(19)
96 #define CTRL1_SPM_VCORE_RESTORE_ACK BIT(20)
97 #define CTRL1_SPM_PMIC_INTERNAL_ACK BIT(21)
98 #define CTRL1_PMIC_IRQ_REQ_EN BIT(22)
99 #define CTRL1_WDT_KICK_P BIT(23)
100 #define CTRL1_FORCE_DDREN_WAKE BIT(24)
101 #define CTRL1_FORCE_F26M_WAKE BIT(25)
102 #define CTRL1_FORCE_APSRC_WAKE BIT(26)
103 #define CTRL1_FORCE_INFRA_WAKE BIT(27)
104 #define CTRL1_FORCE_VRF18_WAKE BIT(28)
105 #define CTRL1_FORCE_VCORE_WAKE BIT(29)
106 #define CTRL1_FORCE_EMI_WAKE BIT(30)
107 #define CTRL1_FORCE_PMIC_WAKE BIT(31)
110 #define CTRL2_MD32PCM_IRQ_TRIG_BIT BIT(31)
113 #define STA0_SRCCLKENI0 BIT(0)
114 #define STA0_SRCCLKENI1 BIT(1)
115 #define STA0_MD_SRCCLKENA BIT(2)
116 #define STA0_MD_SRCCLKENA1 BIT(3)
117 #define STA0_MD_DDREN_REQ BIT(4)
118 #define STA0_CONN_DDREN_REQ BIT(5)
119 #define STA0_SSPM_SRCCLKENA BIT(6)
120 #define STA0_SSPM_APSRC_REQ BIT(7)
121 #define STA0_MD_STATE BIT(8)
122 #define STA0_RC2SPM_SRCCLKENO_0_ACK BIT(9)
123 #define STA0_MM_STATE BIT(10)
124 #define STA0_SSPM_STATE BIT(11)
125 #define STA0_CPUEB_STATE BIT(12)
126 #define STA0_CONN_STATE BIT(13)
127 #define STA0_CONN_VCORE_REQ BIT(14)
128 #define STA0_CONN_SRCCLKENA BIT(15)
129 #define STA0_CONN_SRCCLKENB BIT(16)
130 #define STA0_CONN_APSRC_REQ BIT(17)
131 #define STA0_SCP_STATE BIT(18)
132 #define STA0_CSYSPWRUPREQ BIT(19)
133 #define STA0_PWRAP_SLEEP_ACK BIT(20)
134 #define STA0_DPM_STATE BIT(21)
135 #define STA0_AUDIO_DSP_STATE BIT(22)
136 #define STA0_PMIC_IRQ_ACK BIT(23)
137 #define STA0_RESERVED_BIT_24 BIT(24)
138 #define STA0_RESERVED_BIT_25 BIT(25)
139 #define STA0_RESERVED_BIT_26 BIT(26)
140 #define STA0_DVFS_STATE BIT(27)
141 #define STA0_RESERVED_BIT_28 BIT(28)
142 #define STA0_RESERVED_BIT_29 BIT(29)
143 #define STA0_SC_HW_S1_ACK_ALL BIT(30)
144 #define STA0_DDREN_STATE BIT(31)
146 #define R12_PCM_TIMER_B BIT(0)
147 #define R12_TWAM_PMSR_DVFSRC_ALCO BIT(1)
148 #define R12_KP_IRQ_B BIT(2)
149 #define R12_APWDT_EVENT_B BIT(3)
150 #define R12_APXGPT_EVENT_B BIT(4)
151 #define R12_CONN2AP_WAKEUP_B BIT(5)
152 #define R12_EINT_EVENT_B BIT(6)
153 #define R12_CONN_WDT_IRQ_B BIT(7)
154 #define R12_CCIF0_EVENT_B BIT(8)
155 #define R12_CCIF1_EVENT_B BIT(9)
156 #define R12_SSPM2SPM_WAKEUP_B BIT(10)
157 #define R12_SCP2SPM_WAKEUP_B BIT(11)
158 #define R12_ADSP2SPM_WAKEUP_B BIT(12)
159 #define R12_PCM_WDT_WAKEUP_B BIT(13)
160 #define R12_USB0_CDSC_B BIT(14)
161 #define R12_USB0_POWERDWN_B BIT(15)
162 #define R12_UART_EVENT_B BIT(16)
163 #define R12_DEBUGTOP_FLAG_IRQ_B BIT(17)
164 #define R12_SYS_TIMER_EVENT_B BIT(18)
165 #define R12_EINT_EVENT_SECURE_B BIT(19)
166 #define R12_AFE_IRQ_MCU_B BIT(20)
167 #define R12_THERM_CTRL_EVENT_B BIT(21)
168 #define R12_SYS_CIRQ_IRQ_B BIT(22)
169 #define R12_PBUS_EVENT_B BIT(23)
170 #define R12_CSYSPWREQ_B BIT(24)
171 #define R12_MD_WDT_B BIT(25)
172 #define R12_AP2AP_PEER_WAKEUP_B BIT(26)
173 #define R12_SEJ_B BIT(27)
174 #define R12_CPU_WAKEUP BIT(28)
175 #define R12_APUSYS_WAKE_HOST_B BIT(29)
176 #define R12_PCIE_WAKE_B BIT(30)
177 #define R12_MSDC_WAKE_B BIT(31)
180 #define PCM_PWRIO_EN_R0 BIT(0)
181 #define PCM_PWRIO_EN_R7 BIT(7)
182 #define PCM_RF_SYNC_R0 BIT(16)
183 #define PCM_RF_SYNC_R6 BIT(22)
184 #define PCM_RF_SYNC_R7 BIT(23)
187 #define PCM_SW_INT0 BIT(0)
188 #define PCM_SW_INT1 BIT(1)
189 #define PCM_SW_INT2 BIT(2)
190 #define PCM_SW_INT3 BIT(3)
191 #define PCM_SW_INT4 BIT(4)
192 #define PCM_SW_INT5 BIT(5)
193 #define PCM_SW_INT6 BIT(6)
194 #define PCM_SW_INT7 BIT(7)
195 #define PCM_SW_INT8 BIT(8)
196 #define PCM_SW_INT9 BIT(9)
208 #define ISRM_TWAM BIT(2)
209 #define ISRM_PCM_RETURN BIT(3)
210 #define ISRM_RET_IRQ0 BIT(8)
211 #define ISRM_RET_IRQ1 BIT(9)
212 #define ISRM_RET_IRQ2 BIT(10)
213 #define ISRM_RET_IRQ3 BIT(11)
214 #define ISRM_RET_IRQ4 BIT(12)
215 #define ISRM_RET_IRQ5 BIT(13)
216 #define ISRM_RET_IRQ6 BIT(14)
217 #define ISRM_RET_IRQ7 BIT(15)
218 #define ISRM_RET_IRQ8 BIT(16)
219 #define ISRM_RET_IRQ9 BIT(17)
229 #define ISRS_TWAM BIT(2)
230 #define ISRS_PCM_RETURN BIT(3)
240 #define WAKE_MISC_PMIC_OUT_B (BIT(19) | BIT(20))
250 #define SPM_INTERNAL_STATUS_HW_S1 BIT(0)