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Searched refs:pll (Results 1 – 14 of 14) sorted by relevance

/optee_os/core/drivers/clk/sam/
H A Dat91_pll.c56 struct clk_pll *pll = clk->priv; in clk_pll_enable() local
57 const struct clk_pll_layout *layout = pll->layout; in clk_pll_enable()
58 const struct clk_pll_charac *charac = pll->charac; in clk_pll_enable()
59 uint8_t id = pll->id; in clk_pll_enable()
68 pllr = io_read32(pll->base + offset); in clk_pll_enable()
72 status = io_read32(pll->base + AT91_PMC_SR); in clk_pll_enable()
74 (div == pll->div && mul == pll->mul)) in clk_pll_enable()
78 out = charac->out[pll->range]; in clk_pll_enable()
81 io_clrsetbits32(pll->base + AT91_PMC_PLLICPR, PLL_ICPR_MASK(id), in clk_pll_enable()
82 charac->icpll[pll->range] << in clk_pll_enable()
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H A Dsub.mk14 srcs-$(CFG_SAMA7G5) += clk-sam9x60-pll.c phy-sama7-utmi-clk.c sama7g5_clk.c
/optee_os/core/arch/arm/plat-rockchip/
H A Dcru.h39 #define CRU_PLL_CON0(pll) ((pll) * 0x0c + 0x0) argument
40 #define CRU_PLL_CON1(pll) ((pll) * 0x0c + 0x4) argument
41 #define CRU_PLL_CON2(pll) ((pll) * 0x0c + 0x8) argument
47 #define PLL_MODE_BIT(pll) ((pll) * 4) argument
48 #define PLL_MODE_MSK(pll) BIT(PLL_MODE_BIT(pll)) argument
49 #define PLL_SLOW_MODE(pll) BITS_WITH_WMASK(0, 1, PLL_MODE_BIT(pll)) argument
50 #define PLL_NORM_MODE(pll) BITS_WITH_WMASK(1, 1, PLL_MODE_BIT(pll)) argument
H A Dpsci_rk322x.c85 static void pll_power_down(uint32_t pll) in pll_power_down() argument
89 io_write32(va_base + CRU_MODE_CON, PLL_SLOW_MODE(pll)); in pll_power_down()
90 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_DOWN); in pll_power_down()
93 static void pll_power_up(uint32_t pll) in pll_power_up() argument
97 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_UP); in pll_power_up()
100 static void pll_wait_lock(uint32_t pll) in pll_wait_lock() argument
105 while (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK) && in pll_wait_lock()
111 if (!(io_read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK)) { in pll_wait_lock()
112 EMSG("PLL can't lock, index = %" PRIu32, pll); in pll_wait_lock()
/optee_os/core/arch/arm/dts/
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi110 pll1: st,pll-1 {
111 st,pll = <&pll1_cfg_1200Mhz>;
124 pll2: st,pll-2 {
125 st,pll = <&pll2_cfg_600Mhz>;
133 pll3: st,pll-3 {
134 st,pll = <&pll3_cfg_400Mhz>;
142 pll4: st,pll-4 {
143 st,pll = <&pll4_cfg_1200Mhz>;
151 pll5: st,pll-5 {
152 st,pll = <&pll5_cfg_532Mhz>;
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H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi110 pll1: st,pll-1 {
111 st,pll = <&pll1_cfg_1200MHz>;
124 pll2: st,pll-2 {
125 st,pll = <&pll2_cfg_400MHz>;
133 pll4: st,pll-4 {
134 st,pll = <&pll4_cfg_1200MHz>;
142 pll5: st,pll-5 {
143 st,pll = <&pll5_cfg_532MHz>;
151 pll6: st,pll-6 {
152 st,pll = <&pll6_cfg_500MHz>;
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H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi117 pll1: st,pll-1 {
118 st,pll = <&pll1_cfg_1200Mhz>;
131 pll2: st,pll-2 {
132 st,pll = <&pll2_cfg_600Mhz>;
140 pll3: st,pll-3 {
141 st,pll = <&pll3_cfg_800Mhz>;
154 pll4: st,pll-4 {
155 st,pll = <&pll4_cfg_1200Mhz>;
163 pll5: st,pll-5 {
164 st,pll = <&pll5_cfg_532Mhz>;
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H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi117 pll1: st,pll-1 {
118 st,pll = <&pll1_cfg_1200Mhz>;
131 pll2: st,pll-2 {
132 st,pll = <&pll2_cfg_600Mhz>;
140 pll3: st,pll-3 {
141 st,pll = <&pll3_cfg_800Mhz>;
154 pll4: st,pll-4 {
155 st,pll = <&pll4_cfg_1200Mhz>;
163 pll5: st,pll-5 {
164 st,pll = <&pll5_cfg_532Mhz>;
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H A Dstm32mp135f-dk.dts430 pll1: st,pll@0 {
431 compatible = "st,stm32mp1-pll";
434 st,pll = <&pll1_cfg1>;
453 pll2: st,pll@1 {
454 compatible = "st,stm32mp1-pll";
457 st,pll = <&pll2_cfg1>;
466 pll3: st,pll@2 {
467 compatible = "st,stm32mp1-pll";
470 st,pll = <&pll3_cfg1>;
479 pll4: st,pll@3 {
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H A Dstm32mp215f-dk.dts32 st,pll = <&pll1_cfg_1500MHz>;
38 st,pll = <&pll1_cfg_1200MHz>;
/optee_os/core/drivers/clk/
H A Dclk-stm32mp13.c92 struct stm32_pll_dt_cfg *pll; member
1080 static int clk_stm32_pll_compute_cfgr1(const struct stm32_clk_pll *pll, in clk_stm32_pll_compute_cfgr1() argument
1091 if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) || in clk_stm32_pll_compute_cfgr1()
1092 (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) in clk_stm32_pll_compute_cfgr1()
1097 if (pll->plltype == PLL_800 && refclk >= 8000000U) in clk_stm32_pll_compute_cfgr1()
1128 const struct stm32_clk_pll *pll, in clk_stm32_is_pll_config_on_the_fly() argument
1132 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_is_pll_config_on_the_fly()
1140 ret = clk_stm32_pll_compute_cfgr1(pll, vco, &value); in clk_stm32_is_pll_config_on_the_fly()
1145 if (sel != stm32_mux_get_parent(pll->mux_id)) { in clk_stm32_is_pll_config_on_the_fly()
1183 const struct stm32_clk_pll *pll, in clk_stm32_pll_config_vco() argument
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H A Dclk-stm32mp15.c661 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) in stm32mp1_pll_get_fref() argument
663 uint32_t selr = io_read32(stm32_rcc_base() + pll->rckxselr); in stm32mp1_pll_get_fref()
666 return osc_frequency(pll->refclk[src]); in stm32mp1_pll_get_fref()
675 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) in stm32mp1_pll_get_fvco() argument
684 cfgr1 = io_read32(stm32_rcc_base() + pll->pllxcfgr1); in stm32mp1_pll_get_fvco()
685 fracr = io_read32(stm32_rcc_base() + pll->pllxfracr); in stm32mp1_pll_get_fvco()
690 refclk = stm32mp1_pll_get_fref(pll); in stm32mp1_pll_get_fvco()
718 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); in stm32mp1_read_pll_freq() local
726 cfgr2 = io_read32(stm32_rcc_base() + pll->pllxcfgr2); in stm32mp1_read_pll_freq()
729 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); in stm32mp1_read_pll_freq()
H A Dclk-stm32mp21.c188 struct stm32_pll_dt_cfg *pll; member
1097 struct stm32_pll_dt_cfg *pll) in clk_stm32_parse_pll_fdt() argument
1111 if (fdt_read_uint32_array(fdt, subnode_pll, "cfg", pll->cfg, PLLCFG_NB)) in clk_stm32_parse_pll_fdt()
1114 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", pll->csg, in clk_stm32_parse_pll_fdt()
1117 pll->csg_enabled = (err == 0); in clk_stm32_parse_pll_fdt()
1125 pll->enabled = true; in clk_stm32_parse_pll_fdt()
1127 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0); in clk_stm32_parse_pll_fdt()
1129 if (fdt_read_uint32(fdt, subnode_pll, "src", &pll->src)) in clk_stm32_parse_pll_fdt()
1143 struct stm32_pll_dt_cfg *pll = pdata->pll + i; in stm32_clk_parse_fdt_all_pll() local
1157 if (clk_stm32_parse_pll_fdt(fdt, subnode, pll)) in stm32_clk_parse_fdt_all_pll()
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H A Dclk-stm32mp25.c133 struct stm32_pll_dt_cfg *pll; member
1116 struct stm32_pll_dt_cfg *pll) in clk_stm32_parse_pll_fdt() argument
1130 if (fdt_read_uint32_array(fdt, subnode_pll, "cfg", pll->cfg, PLLCFG_NB)) in clk_stm32_parse_pll_fdt()
1133 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", pll->csg, in clk_stm32_parse_pll_fdt()
1136 pll->csg_enabled = (err == 0); in clk_stm32_parse_pll_fdt()
1144 pll->enabled = true; in clk_stm32_parse_pll_fdt()
1146 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0); in clk_stm32_parse_pll_fdt()
1148 if (fdt_read_uint32(fdt, subnode_pll, "src", &pll->src)) in clk_stm32_parse_pll_fdt()
1162 struct stm32_pll_dt_cfg *pll = pdata->pll + i; in stm32_clk_parse_fdt_all_pll() local
1172 if (clk_stm32_parse_pll_fdt(fdt, subnode, pll)) in stm32_clk_parse_fdt_all_pll()
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