xref: /optee_os/core/arch/arm/dts/stm32mp215f-dk-ca35tdcid-rcc.dtsi (revision d8faf33f0a3a3dc74246f728d31d0c9dd1095e1f)

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
 */

/*
 * STM32MP21 Clock tree device tree configuration
 */

&clk_hse {
	clock-frequency = <40000000>;
};

&clk_hsi {
	clock-frequency = <64000000>;
};

&clk_lse {
	clock-frequency = <32768>;
};

&clk_lsi {
	clock-frequency = <32000>;
};

&clk_msi {
	clock-frequency = <16000000>;
};

&rcc {
	st,busclk = <
		DIV_CFG(DIV_LSMCU, 1)
		DIV_CFG(DIV_APB1, 0)
		DIV_CFG(DIV_APB2, 0)
		DIV_CFG(DIV_APB3, 0)
		DIV_CFG(DIV_APB4, 0)
		DIV_CFG(DIV_APB5, 0)
		DIV_CFG(DIV_APBDBG, 0)
	>;

	st,flexgen = <
		FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 3)
		FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
		FLEXGEN_CFG(3, XBAR_SRC_PLL4, 0, 2)
		FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
		FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
		FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1)
		FLEXGEN_CFG(7, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
		FLEXGEN_CFG(9, XBAR_SRC_HSI_KER, 0, 0)
		FLEXGEN_CFG(10, XBAR_SRC_PLL7, 0, 16)
		FLEXGEN_CFG(11, XBAR_SRC_PLL7, 0, 16)
		FLEXGEN_CFG(12, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(13, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(14, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(16, XBAR_SRC_PLL7, 0, 16)
		FLEXGEN_CFG(17, XBAR_SRC_PLL5, 0, 3)
		FLEXGEN_CFG(18, XBAR_SRC_HSI_KER, 0, 0)
		FLEXGEN_CFG(19, XBAR_SRC_HSI_KER, 0, 0)
		FLEXGEN_CFG(20, XBAR_SRC_HSI_KER, 0, 0)
		FLEXGEN_CFG(21, XBAR_SRC_PLL7, 0, 16)
		FLEXGEN_CFG(22, XBAR_SRC_PLL7, 0, 16)
		FLEXGEN_CFG(23, XBAR_SRC_PLL7, 0, 16)
		FLEXGEN_CFG(24, XBAR_SRC_PLL7, 0, 16)
		FLEXGEN_CFG(25, XBAR_SRC_PLL7, 0, 16)
		FLEXGEN_CFG(26, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(27, XBAR_SRC_PLL8, 0, 3)
		FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1)
		FLEXGEN_CFG(30, XBAR_SRC_HSE_KER, 0, 1)
		FLEXGEN_CFG(31, XBAR_SRC_PLL5, 0, 19)
		FLEXGEN_CFG(33, XBAR_SRC_HSE_KER, 0, 0)
		FLEXGEN_CFG(36, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(37, XBAR_SRC_PLL5, 0, 3)
		FLEXGEN_CFG(38, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(39, XBAR_SRC_MSI_KER, 0, 0)
		FLEXGEN_CFG(40, XBAR_SRC_LSE, 0, 0)
		FLEXGEN_CFG(41, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(42, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(43, XBAR_SRC_PLL4, 0, 23)
		FLEXGEN_CFG(44, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(45, XBAR_SRC_PLL4, 0, 2)
		FLEXGEN_CFG(46, XBAR_SRC_PLL5, 0, 3)
		FLEXGEN_CFG(47, XBAR_SRC_PLL5, 0, 3)
		FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
		FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(53, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(54, XBAR_SRC_PLL6, 0, 9)
		FLEXGEN_CFG(55, XBAR_SRC_PLL6, 0, 3)
		FLEXGEN_CFG(56, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(57, XBAR_SRC_HSE_KER, 0, 1)
		FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
		FLEXGEN_CFG(61, XBAR_SRC_PLL4, 0, 7)
		FLEXGEN_CFG(62, XBAR_SRC_PLL4, 0, 7)
		FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
	>;

	st,kerclk = <
		MUX_CFG(MUX_ADC1, MUX_ADC1_FLEX46)
		MUX_CFG(MUX_ADC2, MUX_ADC2_FLEX47)
		MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
		MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
		MUX_CFG(MUX_DTS, MUX_DTS_HSE)
		MUX_CFG(MUX_RTC, MUX_RTC_LSE)
		MCO_CFG(MCO1, MUX_MCO1_FLEX61, MCO_OFF)
		MCO_CFG(MCO2, MUX_MCO2_FLEX62, MCO_OFF)
	>;

	pll1: st,pll-1 {
		st,pll = <&pll1_cfg_1200MHz>;

		pll1_cfg_1200MHz: pll1-cfg-1200MHz {
			cfg = <30 1 1 1>;
			src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
		};

		pll1_cfg_1500MHz: pll1-cfg-1500MHz {
			cfg = <75 2 1 1>;
			src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
		};
	};

	pll2: st,pll-2 {
		st,pll = <&pll2_cfg_400MHz>;

		pll2_cfg_400MHz: pll2-cfg-400MHz {
			cfg = <20 1 1 2>;
			src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
		};
	};

	pll4: st,pll-4 {
		st,pll = <&pll4_cfg_1200MHz>;

		pll4_cfg_1200MHz: pll4-cfg-1200MHz {
			cfg = <30 1 1 1>;
			src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
		};
	};

	pll5: st,pll-5 {
		st,pll = <&pll5_cfg_532MHz>;

		pll5_cfg_532MHz: pll5-cfg-532MHz {
			cfg = <133 5 1 2>;
			src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
		};
	};

	pll6: st,pll-6 {
		st,pll = <&pll6_cfg_500MHz>;

		pll6_cfg_500MHz: pll6-cfg-500MHz {
			cfg = <25 1 1 2>;
			src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>;
		};
	};

	pll7: st,pll-7 {
		st,pll = <&pll7_cfg_835_51172MHz>;

		pll7_cfg_835_51172MHz: pll7-cfg-835-51172MHz {
			cfg = <167 4 1 2>;
			src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
			frac = < 0x1A3337 >;
		};
	};

	pll8: st,pll-8 {
		st,pll = <&pll8_cfg_594MHz>;

		pll8_cfg_594MHz: pll8-cfg-594MHz {
			cfg = <297 5 1 4>;
			src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
		};
	};
};