plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized sta

plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized status and control (SSC) registers

This path removes the confusion between SSC and subsystem (SS).

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Co-developed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: cosmetic fixes for STM32MP25 clock driver

Cosmetic fixes to align STM32MP21 and STM32MP25 clock drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by

clk: stm32mp25: cosmetic fixes for STM32MP25 clock driver

Cosmetic fixes to align STM32MP21 and STM32MP25 clock drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
becau

clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
because the clkext2f frequency of 400MHz is not supported.

This patch also rename the function stm32mp2_a35_ss_on_hsi to
stm32mp2_a35_ss_on_bypass to be aligned with reference manual.

Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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clk: stm32mp25: configure STGEN flexgen in .enable ops

STGEN flexgen is skipped during RCC probe to prevent misalignment
between stgen_clk frequency and STGEN register. Configure the STGEN
flexgen i

clk: stm32mp25: configure STGEN flexgen in .enable ops

STGEN flexgen is skipped during RCC probe to prevent misalignment
between stgen_clk frequency and STGEN register. Configure the STGEN
flexgen in the .enable ops so that it is configured after the STGEN
itself is configured and started.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: add support for RIF configuration application

This driver now implements RIF configuration for RCC, which is a RIF
aware IP. It means that the RCC driver is in charge of configuring

clk: stm32mp25: add support for RIF configuration application

This driver now implements RIF configuration for RCC, which is a RIF
aware IP. It means that the RCC driver is in charge of configuring its
own RIF restrictions and that the RCC has dedicated RIF configuration
registers.

To avoid issues when manipulating clocks during OP-TEE boot or low-power
sequences, apply the RIF configuration for RCC resources at
driver_init_late level.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: don't mix error codes in stm32mp25 driver

Don't mix error codes in stm32mp25 clock driver: some function return
a TEE_Result value, some return a 0/-1 integer value.

Signed-off-by: Et

drivers: clk: don't mix error codes in stm32mp25 driver

Don't mix error codes in stm32mp25 clock driver: some function return
a TEE_Result value, some return a 0/-1 integer value.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: fix error cases in STM32MP25 clocks

Fix missing test on some function return code in stm32mp25 clock
driver.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by

drivers: clk: fix error cases in STM32MP25 clocks

Fix missing test on some function return code in stm32mp25 clock
driver.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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clk: stm32mp25: Introduce STM32MP25 clocks platform

This driver is based on clk-stm32-core API to manage STM32 gates, dividers
and muxes.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st

clk: stm32mp25: Introduce STM32MP25 clocks platform

This driver is based on clk-stm32-core API to manage STM32 gates, dividers
and muxes.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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