1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/clock/stm32mp13-clksrc.h> 10#include <dt-bindings/firewall/stm32mp13-tzc400.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/stm32mp_gpio.h> 13#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 14#include <dt-bindings/tamper/st,stm32mp13-tamp.h> 15#include "stm32mp135.dtsi" 16#include "stm32mp13xf.dtsi" 17#include "stm32mp13-pinctrl.dtsi" 18 19/ { 20 model = "STMicroelectronics STM32MP135F-DK Discovery Board"; 21 compatible = "st,stm32mp135f-dk", "st,stm32mp135"; 22 23 aliases { 24 serial0 = &uart4; 25 serial1 = &usart1; 26 }; 27 28 chosen { 29 stdout-path = "serial0:115200n8"; 30 }; 31 32 memory@c0000000 { 33 device_type = "memory"; 34 reg = <0xc0000000 0x20000000>; 35 }; 36 37 reserved-memory { 38 #address-cells = <1>; 39 #size-cells = <1>; 40 ranges; 41 42 optee_framebuffer: optee-framebuffer@dd000000 { 43 /* Secure framebuffer memory */ 44 reg = <0xdd000000 0x1000000>; 45 st,protreg = <DT_TZC_REGION_S_RDWR 0>; 46 no-map; 47 }; 48 }; 49 50 vin: vin { 51 compatible = "regulator-fixed"; 52 regulator-name = "vin"; 53 regulator-min-microvolt = <5000000>; 54 regulator-max-microvolt = <5000000>; 55 regulator-always-on; 56 }; 57 58 v3v3_ao: v3v3_ao { 59 compatible = "regulator-fixed"; 60 regulator-name = "v3v3_ao"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 regulator-always-on; 64 }; 65}; 66 67&bsec { 68 board_id: board_id@f0 { 69 reg = <0xf0 0x4>; 70 st,non-secure-otp; 71 }; 72}; 73 74&cpu0 { 75 cpu-supply = <&vddcpu>; 76}; 77 78&etzpc { 79 st,decprot = 80 <DECPROT(STM32MP1_ETZPC_ADC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 81 <DECPROT(STM32MP1_ETZPC_ADC2_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 82 <DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 83 <DECPROT(STM32MP1_ETZPC_CRYP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 84 <DECPROT(STM32MP1_ETZPC_DCMIPP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 85 <DECPROT(STM32MP1_ETZPC_DDRCTRLPHY_ID, DECPROT_NS_R_S_W, DECPROT_UNLOCK)>, 86 <DECPROT(STM32MP1_ETZPC_ETH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 87 <DECPROT(STM32MP1_ETZPC_ETH2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 88 <DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 89 <DECPROT(STM32MP1_ETZPC_HASH_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 90 <DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 91 <DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 92 <DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 93 <DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 94 <DECPROT(STM32MP1_ETZPC_LPTIM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 95 <DECPROT(STM32MP1_ETZPC_LPTIM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 96 <DECPROT(STM32MP1_ETZPC_LTDC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 97 <DECPROT(STM32MP1_ETZPC_MCE_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 98 <DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 99 <DECPROT(STM32MP1_ETZPC_PKA_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 100 <DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 101 <DECPROT(STM32MP1_ETZPC_RNG_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 102 <DECPROT(STM32MP1_ETZPC_SAES_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 103 <DECPROT(STM32MP1_ETZPC_SDMMC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 104 <DECPROT(STM32MP1_ETZPC_SDMMC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 105 <DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 106 <DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 107 <DECPROT(STM32MP1_ETZPC_SRAM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 108 <DECPROT(STM32MP1_ETZPC_SRAM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 109 <DECPROT(STM32MP1_ETZPC_SRAM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 110 <DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 111 <DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 112 <DECPROT(STM32MP1_ETZPC_TIM13_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 113 <DECPROT(STM32MP1_ETZPC_TIM14_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 114 <DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_S_RW, DECPROT_UNLOCK)>, 115 <DECPROT(STM32MP1_ETZPC_TIM16_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 116 <DECPROT(STM32MP1_ETZPC_TIM17_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 117 <DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 118 <DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 119 <DECPROT(STM32MP1_ETZPC_USBPHYCTRL_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 120 <DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>; 121}; 122 123&gpioa { 124 st,protreg = <TZPROT(6)>; 125}; 126 127&gpiob { 128 st,protreg = <TZPROT(9)>; 129}; 130 131&gpiod { 132 st,protreg = <TZPROT(7)>; 133}; 134 135&gpioe { 136 st,protreg = <TZPROT(15)>; 137}; 138 139&hash { 140 status = "okay"; 141}; 142 143&i2c4 { 144 pinctrl-names = "default"; 145 pinctrl-0 = <&i2c4_pins_a>; 146 i2c-scl-rising-time-ns = <185>; 147 i2c-scl-falling-time-ns = <20>; 148 clock-frequency = <400000>; 149 status = "okay"; 150 151 pmic: stpmic@33 { 152 compatible = "st,stpmic1"; 153 reg = <0x33>; 154 status = "okay"; 155 st,wakeup-pin-number = <1>; 156 st,notif-it-id = <0>; 157 158 regulators { 159 compatible = "st,stpmic1-regulators"; 160 buck1-supply = <&vin>; 161 buck2-supply = <&vin>; 162 buck3-supply = <&vin>; 163 buck4-supply = <&vin>; 164 ldo1-supply = <&vin>; 165 ldo4-supply = <&vin>; 166 ldo5-supply = <&vin>; 167 ldo6-supply = <&vin>; 168 vref_ddr-supply = <&vin>; 169 pwr_sw1-supply = <&bst_out>; 170 pwr_sw2-supply = <&v3v3_ao>; 171 172 vddcpu: buck1 { 173 regulator-name = "vddcpu"; 174 regulator-min-microvolt = <1250000>; 175 regulator-max-microvolt = <1350000>; 176 regulator-always-on; 177 regulator-over-current-protection; 178 179 lp-stop { 180 regulator-suspend-microvolt = <1250000>; 181 }; 182 lplv-stop { 183 regulator-suspend-microvolt = <900000>; 184 }; 185 lplv-stop2 { 186 regulator-off-in-suspend; 187 }; 188 standby-ddr-sr { 189 regulator-off-in-suspend; 190 }; 191 standby-ddr-off { 192 regulator-off-in-suspend; 193 }; 194 }; 195 196 vdd_ddr: buck2 { 197 regulator-name = "vdd_ddr"; 198 regulator-min-microvolt = <1350000>; 199 regulator-max-microvolt = <1350000>; 200 regulator-always-on; 201 regulator-over-current-protection; 202 203 standby-ddr-off { 204 regulator-off-in-suspend; 205 }; 206 }; 207 208 vdd: buck3 { 209 regulator-name = "vdd"; 210 regulator-min-microvolt = <3300000>; 211 regulator-max-microvolt = <3300000>; 212 regulator-always-on; 213 st,mask-reset; 214 regulator-over-current-protection; 215 }; 216 217 vddcore: buck4 { 218 regulator-name = "vddcore"; 219 regulator-min-microvolt = <1250000>; 220 regulator-max-microvolt = <1250000>; 221 regulator-always-on; 222 regulator-over-current-protection; 223 224 lplv-stop { 225 regulator-suspend-microvolt = <900000>; 226 }; 227 lplv-stop2 { 228 regulator-suspend-microvolt = <900000>; 229 }; 230 standby-ddr-sr { 231 regulator-off-in-suspend; 232 }; 233 standby-ddr-off { 234 regulator-off-in-suspend; 235 }; 236 }; 237 238 vdd_adc: ldo1 { 239 regulator-name = "vdd_adc"; 240 regulator-min-microvolt = <3300000>; 241 regulator-max-microvolt = <3300000>; 242 243 standby-ddr-sr { 244 regulator-off-in-suspend; 245 }; 246 standby-ddr-off { 247 regulator-off-in-suspend; 248 }; 249 }; 250 251 unused1: ldo2 { 252 regulator-name = "ldo2"; 253 }; 254 255 unused2: ldo3 { 256 regulator-name = "ldo3"; 257 }; 258 259 vdd_usb: ldo4 { 260 regulator-name = "vdd_usb"; 261 regulator-min-microvolt = <3300000>; 262 regulator-max-microvolt = <3300000>; 263 264 standby-ddr-sr { 265 regulator-off-in-suspend; 266 }; 267 standby-ddr-off { 268 regulator-off-in-suspend; 269 }; 270 }; 271 272 vdd_sd: ldo5 { 273 regulator-name = "vdd_sd"; 274 regulator-min-microvolt = <3300000>; 275 regulator-max-microvolt = <3300000>; 276 regulator-boot-on; 277 278 standby-ddr-sr { 279 regulator-off-in-suspend; 280 }; 281 standby-ddr-off { 282 regulator-off-in-suspend; 283 }; 284 }; 285 286 v1v8_periph: ldo6 { 287 regulator-name = "v1v8_periph"; 288 regulator-min-microvolt = <1800000>; 289 regulator-max-microvolt = <1800000>; 290 291 standby-ddr-sr { 292 regulator-off-in-suspend; 293 }; 294 standby-ddr-off { 295 regulator-off-in-suspend; 296 }; 297 }; 298 299 vref_ddr: vref_ddr { 300 regulator-name = "vref_ddr"; 301 regulator-always-on; 302 303 standby-ddr-sr { 304 regulator-off-in-suspend; 305 }; 306 standby-ddr-off { 307 regulator-off-in-suspend; 308 }; 309 }; 310 311 bst_out: boost { 312 regulator-name = "bst_out"; 313 }; 314 315 v3v3_sw: pwr_sw2 { 316 regulator-name = "v3v3_sw"; 317 regulator-active-discharge = <1>; 318 regulator-min-microvolt = <3300000>; 319 regulator-max-microvolt = <3300000>; 320 }; 321 }; 322 }; 323}; 324 325&iwdg1 { 326 timeout-sec = <32>; 327 status = "okay"; 328}; 329 330&oem_enc_key { 331 st,non-secure-otp-provisioning; 332}; 333 334&pka { 335 status = "okay"; 336}; 337 338&pwr_regulators { 339 vdd-supply = <&vdd>; 340 vdd_3v3_usbfs-supply = <&vdd_usb>; 341}; 342 343&rcc { 344 compatible = "st,stm32mp13-rcc", "syscon"; 345 346 st,clksrc = < 347 CLK_MPU_PLL1P 348 CLK_AXI_PLL2P 349 CLK_MLAHBS_PLL3 350 CLK_RTC_LSE 351 CLK_MCO1_HSE 352 CLK_MCO2_DISABLED 353 CLK_CKPER_HSE 354 CLK_ETH1_PLL4P 355 CLK_ETH2_PLL4P 356 CLK_SDMMC1_PLL4P 357 CLK_SDMMC2_PLL4P 358 CLK_STGEN_HSE 359 CLK_USBPHY_HSE 360 CLK_I2C4_HSI 361 CLK_I2C5_HSI 362 CLK_USBO_USBPHY 363 CLK_ADC2_CKPER 364 CLK_I2C12_HSI 365 CLK_UART1_HSI 366 CLK_UART2_HSI 367 CLK_UART35_HSI 368 CLK_UART4_HSI 369 CLK_UART6_HSI 370 CLK_UART78_HSI 371 CLK_SAES_AXI 372 CLK_DCMIPP_PLL2Q 373 CLK_LPTIM3_PCLK3 374 CLK_RNG1_PLL4R 375 >; 376 377 st,clkdiv = < 378 DIV(DIV_MPU, 1) 379 DIV(DIV_AXI, 0) 380 DIV(DIV_MLAHB, 0) 381 DIV(DIV_APB1, 1) 382 DIV(DIV_APB2, 1) 383 DIV(DIV_APB3, 1) 384 DIV(DIV_APB4, 1) 385 DIV(DIV_APB5, 2) 386 DIV(DIV_APB6, 1) 387 DIV(DIV_RTC, 0) 388 DIV(DIV_MCO1, 0) 389 DIV(DIV_MCO2, 0) 390 >; 391 392 st,pll_vco { 393 pll1_vco_2000Mhz: pll1-vco-2000Mhz { 394 src = <CLK_PLL12_HSE>; 395 divmn = <1 82>; 396 frac = <0xAAA>; 397 }; 398 399 pll1_vco_1800Mhz: pll1-vco-1800Mhz { 400 src = <CLK_PLL12_HSE>; 401 divmn = <1 74>; 402 frac = <0>; 403 }; 404 405 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 406 src = <CLK_PLL12_HSE>; 407 divmn = <2 80>; 408 frac = <0x800>; 409 }; 410 411 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 412 src = <CLK_PLL12_HSE>; 413 divmn = <2 65>; 414 frac = <0x1400>; 415 }; 416 417 pll3_vco_417Mhz: pll3-vco-417Mhz { 418 src = <CLK_PLL3_HSE>; 419 divmn = <1 33>; 420 frac = <0x1a04>; 421 }; 422 423 pll4_vco_600Mhz: pll4-vco-600Mhz { 424 src = <CLK_PLL4_HSE>; 425 divmn = <1 49>; 426 }; 427 }; 428 429 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 430 pll1: st,pll@0 { 431 compatible = "st,stm32mp1-pll"; 432 reg = <0>; 433 434 st,pll = <&pll1_cfg1>; 435 436 pll1_cfg1: pll1_cfg1 { 437 st,pll_vco = <&pll1_vco_1300Mhz>; 438 st,pll_div_pqr = <0 1 1>; 439 }; 440 441 pll1_cfg2: pll1_cfg2 { 442 st,pll_vco = <&pll1_vco_2000Mhz>; 443 st,pll_div_pqr = <0 1 1>; 444 }; 445 446 pll1_cfg3: pll1_cfg3 { 447 st,pll_vco = <&pll1_vco_1800Mhz>; 448 st,pll_div_pqr = <0 1 1>; 449 }; 450 }; 451 452 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ 453 pll2: st,pll@1 { 454 compatible = "st,stm32mp1-pll"; 455 reg = <1>; 456 457 st,pll = <&pll2_cfg1>; 458 459 pll2_cfg1: pll2_cfg1 { 460 st,pll_vco = <&pll2_vco_1066Mhz>; 461 st,pll_div_pqr = <1 1 0>; 462 }; 463 }; 464 465 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 466 pll3: st,pll@2 { 467 compatible = "st,stm32mp1-pll"; 468 reg = <2>; 469 470 st,pll = <&pll3_cfg1>; 471 472 pll3_cfg1: pll3_cfg1 { 473 st,pll_vco = <&pll3_vco_417Mhz>; 474 st,pll_div_pqr = <1 16 36>; 475 }; 476 }; 477 478 /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ 479 pll4: st,pll@3 { 480 compatible = "st,stm32mp1-pll"; 481 reg = <3>; 482 st,pll = <&pll4_cfg1>; 483 484 pll4_cfg1: pll4_cfg1 { 485 st,pll_vco = <&pll4_vco_600Mhz>; 486 st,pll_div_pqr = <11 59 11>; 487 }; 488 }; 489 490 st,clk_opp { 491 /* CK_MPU clock config for MP13 */ 492 st,ck_mpu { 493 cfg_1 { 494 hz = <650000000>; 495 st,clksrc = <CLK_MPU_PLL1P>; 496 st,pll = <&pll1_cfg1>; 497 }; 498 499 cfg_2 { 500 hz = <1000000000>; 501 st,clksrc = <CLK_MPU_PLL1P>; 502 st,pll = <&pll1_cfg2>; 503 }; 504 505 cfg_3 { 506 hz = <900000000>; 507 st,clksrc = <CLK_MPU_PLL1P>; 508 st,pll = <&pll1_cfg3>; 509 }; 510 }; 511 }; 512}; 513 514&rng { 515 status = "okay"; 516 clock-error-detect; 517}; 518 519&saes { 520 status = "okay"; 521}; 522 523&sdmmc1_io { 524 vddsd1-supply = <&vdd>; 525}; 526 527&sdmmc2_io { 528 vddsd2-supply = <&vdd>; 529}; 530 531&tamp { 532 st,tamp-passive-nb-sample = <4>; 533 st,tamp-passive-sample-clk-div = <16384>; 534 wakeup-source; 535 536 /* Tamper button */ 537 tamp-button { 538 tamper-gpios = <&gpioa 6 0>; 539 st,tamp-mode = <TAMPER_CONFIRMED_MODE>; 540 st,tamp-id = <2>; 541 status = "okay"; 542 }; 543 544 /* Connect pin8 and pin22 from CN8 */ 545 tamp-active { 546 tamper-gpios = <&gpioc 0 0>, <&gpioi 0 0>; 547 st,tamp-mode = <TAMPER_CONFIRMED_MODE>; 548 st,tamp-id = <3>, <1>; 549 status = "disabled"; 550 }; 551}; 552 553&tzc400 { 554 memory-region = <&optee_framebuffer>; 555}; 556 557&uart4 { 558 pinctrl-names = "default"; 559 pinctrl-0 = <&uart4_pins_a>; 560 status = "okay"; 561}; 562 563&usart1 { 564 pinctrl-names = "default"; 565 pinctrl-0 = <&usart1_pins_a>; 566 uart-has-rtscts; 567 status = "disabled"; 568}; 569